Other Parts Discussed in Thread: ADS127L01EVM, ADS127L01
How two ADC ADS127L01EVM ADCs can be synchronized so that the sampled data from the ADCs are phase aligned ?
Thanks a lot in advance for your help !
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Other Parts Discussed in Thread: ADS127L01EVM, ADS127L01
How two ADC ADS127L01EVM ADCs can be synchronized so that the sampled data from the ADCs are phase aligned ?
Thanks a lot in advance for your help !
Hello Sufian,
Welcome to the TI E2E Community.
Unfortunately, the EVM software does not support synchronization of multiple EVM boards. You can, of course, synchronize devices in your own design using the START pin. Please see section 8.4.3 in the ADS127L01 datasheet for more details.
Regards,
Keith Nicholas
Precision ADC Applications
Hello Keith,
Thank you for replying ,
I am Sufyan Sr. | Software Engineer from Mazaya LTD,
Our software supports synchronization of multiple EVM boards.
Is it possible to more details how to sync, I don't have enough knowledge of ADC applications.
Best Regards,
Sufian Sh
Hello Sufyan,
You will need to control both ADS127L01EVM's with a single MCU. I assume you are using your own host MCU to read the data. You can isolate the on-board processors by removing the shunts on J3 of each EVM.
Each EVM provides a clock for the ADC. You can use the clock from one of the EVM's and connect it to both. In other words, use the on-board clock for one of the EVM's, and wire this clock to the other EVM through JP6.
For the rest of the connections, I suggest following Figure 103 in the ADS127L01 datasheet.
After you have both EVM's powered up and connected to your host MCU, you will need to pulse the START pin, connected to both EVM's. The timing requirements in Figure 85 of the datasheet should be followed so that both ADC's will be synchronized to the same master CLK edge.
After synchronization, assuming each device is configured for the same output data rate, the /DRDY pins will be synchronized. You will want to monitor this signal (you only need to monitor one of the DRDY lines since they are now synchronized), either through polling or an interrupt routine. When DRDY transitions from high to low, you can transfer the data from each ADC.
Regards,
Keith