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TPS7A37: Instability issues - part 2

Part Number: TPS7A37
Other Parts Discussed in Thread: TPS63710, LP5907, LP5912

Hi everyone,

Unfortunately, the issues are still here.

Part one of this mess is here

Even worse, i have improved the pcb a bit (at least i think i did) and tried the fixed version of the LDO TPS7A3725 (2.5V) without any luck.

At first everything worked for a few minutes and then trembling and random behaviour started.

I am at a dead end. Designing for months and i got stuck with an LDO instability issue. The last thing i would ever think...

Here is the 6-layer pcb around the TPS7A37XX with the top layer solder paste areas visible

This ^ is the bottom layer. The ground plane is clearly visible.

This ^ is the inner layer 4. Just like bottom layer, the ground plane is the cyan colored area.

This ^ is the inner layer 3. There is no ground plane here. The blue area that you see (not close the edges) is the +5.3V rail that is supplying the TPS7A37XX.

This ^ is the inner layer 2. Again, ground plane is dominant.

This ^ is the inner layer 1. Ground plane is under the feedback loop traces. The yellow trace going downwards is taking the output of the TPS to a pin header.

This ^ is the top layer.

This ^ is the fixed version of the TPS soldered with the FB pin being decoupled by a MLCC 10nF as required by the DS in order to further reduce output noise.

What i find realy strange is that the 2x LP5912, 1x LP5907 and TPS63710 inverter smps are not facing any issues.

Could this be an inherent instability issue? I have already spent $200 for the first prototype pcbs and another $200 for the last set.

What about the critical selection of the MLCC caps?

DS says at p 8.1.1: "In applications where multiple low ESR capacitors are in parallel, ringing may occur when COUT× ESR< 50 nΩ-F.". Can you pls explain that?

I have selected this cap for both input and output: click here.

Have you got any suggestions? Should i be looking for a replacement?

Regards

Manos Tsachalidis

  • Hi Manos,

    Are you now looking at the new set of boards?
    If so, what changes were made between the previous set and the new set?

    Are there any cold solder joints in the RTN or GND path of the linear regulator?
    One of our customers recently had some strange behavior that was resolved once a ground pad was discovered to be intermittent.

    The guidance in the datasheet is describing the output capacitance and the necessary ESR to maintain stability.
    In the characteristic curves of the capacitor, the ESR is around 3m ohms and the capacitance is 10uF.
    So a first order approximation is this provides 30 n-ohm-F.  So, it may be a stability issue.
    You can test this by adding a series resistance with the output capacitance to increase the effective ESR.

    Let us know the results.

    Thanks,

    - Stephen

  • Hi Stephen,

    Thanks for your response.

    Yes these are the new boards.

    Changes were made as far as the second layer is concerned. The output rail +2.5V was passing right underneath the feedback loop traces of the TPS7A3701. That area on the new boards is now having ground underneath. The distance between the top layer and the second layer is only 0.15mm (see here: jlcpcb.com/quote so there is considerable capacitive coupling.

    This ^ is V1.01. The previous boards. Yellow traces is the second layer (first inner layer). Red is the top layer.

    This ^ is V1.02. This is the latest board. Clearly visible that the feedback loop traces are not capacitively coupled with the output even if we re talking a few pf. The input & output caps' GND pads are now very close to each other. All three pins 4, 5 & 6 are now connected on the same trace (see the prev post) unlike the V1.01 where Vin trace was thin.

    As far as solder joints are concerned, they seem to be very good and shiny. It is not that obvious from the screen shot i uploaded in my prev post but i could use some flux and soldering iron to re-do them just in case.

    The output cap is something that troubles me a lot. I was not sure about how to explain the ESR curve. So now i get it that you are referring to the min ESR that the cap has located near the resonance frequency which is, as you noted, around 3mΩ. Turns out, i was not particularly cautious while reading the DS. Paragraph 8.2.1.2 provides a decent explanation.

    Please correct me if i am wrong (just stating my thought - despite the fact that you have already explained this):

    The DS says: 10mΩ@10uFarad => 100nΩ@1Farad

    So in my case: 3mΩ@10uFarad => 100nΩ / (10/3) =  30.3nΩ

    Or i could say: 3mΩ@10uFarad => (inverse rule of 3) (3mΩ * 10uF) / 1F = 3*10^-8Ω = 30nΩ

    I will try to find a cap with a higher ESR and run some tests and get back to you.

    Thanks a lot for the support.

    Regards

    Manos

  • Hi Manos,

    That is correct.

    Adding some miliohms of series impedance may be enough to raise the value to ensure stability.

    Your layout for the second batch of boards is much better, this was a positive improvement to place ground directly underneath the feedback pin.

    Thanks,

    - Stephen

  • Hi Stephen,

    Sorry for the late reply.

    I did not have any components with such ESR and adding some milliohms in series with the output cap seemed nasty.

    I ordered a few components that have an minimum ESR of > 10mΩ @ 4.7uF.

    Finding caps with an ESR > 10mΩ @ 10uF seemed impossible.

    I ordered these KEMET caps with a capacitance of 4.7uF. Please see and confirm if they seem like a good fit.

    Specs: 4.7uF/16V

    Mouser: eu.mouser.com/.../80-C0805C475K4RAUTO

    Simulation: ksim.kemet.com/

    And this:

    Specs: 4.7uF/25V

    Mouser: eu.mouser.com/.../80-C0805C475K3RAUTO

    Simulation: ksim.kemet.com/

    In the meantime i have removed the output cap and the LDO seems to work ok but every now and then it starts being unstable.

    After i applied a thorough cleaning (not that i did not do it again in the past) it has been stable for many hours yesterday and today all day (LT: 20:40 now)

    The +5V & +3.3V LDOs that i have on the same pcb LP5912 & LP5907 are rock steady since day one. Really this TPS7A3701 is giving me the creeps!

    Please have a look and confirm

    Regards

    Manos

  • Hi Stephen,

    After all this time, i have not really ended with a clear conclusion.

    I tried the 4.7uF/25V MLCC that has >10mΩ ESR and the TPS7A3701 went on operating fine as it was without an output cap as per my last msg!

    No more instabilities, no more weird stuff.

    In fact, to investigate deeper i used the 12bit ADC of the uC on the same board destined to check all the voltage rails of the entire system. I wrote a few lines of code in order to check the min and max instantaneous voltage values across a period of many hours >10 so that in case of any instability the values of the TPS output would be recorded as min/max. I adjusted the output voltage at 2.30V with the difference between min/max being close to 15mV both at no load and with a load of 400mA.

    The ADC input is connected to the [SAMPLE+2.5V] label with a 10nF MLCC soldered on top of the R16 to suppress extrinsic noise.

    I really do not know if it was a matter of good cleaning, carelessness, bad grounding on the pcb or anything else that i have overlooked.

    Thanks for your support so far Stephen.

    Regards

    Manos

  • Hi Manos,

    I apologize for the delay in my response.
    I usually reply back within 24 hours, however I am out of the office until December 16th, where I will be back for 1 week until the new year.
    I don't mind continuing to help troubleshoot any power questions you may have, however my replies may be delayed.

    Regarding operating this linear regulator without an output capacitor.  You may be 'getting lucky' right now if it is stable while not meeting the datasheets recommendations.  The datasheet recommendation will consider tolerances and internal die variations, as well as temperature, and load current, when determining the necessary output impedance to maintain stability.  You may not be hitting the corner cases - at this moment - that would result in an unstable linear regulator, when you operate without an output capacitor.  It is therefore better to operate with the output capacitor that meets the datasheet recommendations.  Additionally, if you were to ever experience a load transient for any reason, the output capacitor will handle the initial surge of current before the LDO bandwidth can catch up.  So you want an output capacitor installed in most cases to help with transient responses.

    The capacitors you located will meet the datasheet recommendations from a nominal perspective.
    If this will enter production and experience high volume in sales, a more robust solution would be to add a small amount of series resistance to ensure the datasheet recommendations for stability are always met.

    Regarding the ADC test - I like the idea.  Just keep in mind that with those values of resistors, the thevenin equivalent will be the parallel resistance of 1K and 2K.  With 10nF on the input to the ADC, the internal sampling capacitor is dominated by the 10nF, and you will have a large time constant of tau = 6.67us.  So 5 time constants = 33us.  As a result, you may be filtering the output of the linear regulator and may not see the noise going into the ADC, which includes any oscillations that may exist (hopefully none).  See the following reference, page 131. 

    www.ti.com/.../slyw038c.pdf

    Thanks,

    - Stephen

  • Hi Manos,

    Another idea is that, if this becomes a continuing problem, it may be easier for you to locate your nearest TI sales office and ship a unit or two to our office.  Then I or one of my colleagues can troubleshoot on the bench and provide another level of support.  Of course, there are many reasons why customers cannot ship hardware, and if that is the case for you, that is fine - we can continue our discussion over E2E as well, if you need it.

    Thanks,

    - Stephen

  • Hi Stephen,

    Thank you so much for the response(s). It is really nice to see people being interested to provide support beyond this point.

    My objective was to add the 10nF to suppress noise, as i said in my last.

    If there was any kind of instability that would have been reflected on the min/max recorded values.

    I say this based on the fact that the instability i noticed consisted of fluctuations that, in their majority, were easily recognizable with a naked eye.

    As you calculated, the 10nF would have hidden any instability only if it had the form of "high speed noise" if i can call it that!

    Although i have been designing pcbs since high school (i am 43 now) i often find myself being over excited and eventually carried out resulting in really childish mistakes identified after the pcb fabrication has already progressed. Having said that, i have read again and again numerous app notes regarding pcb design, gnd loops, returns paths (dc & ac) and specifically high speed pcb design during the last year that i have been working on this project.

    In order to erase any doubts of the 10nF cap hiding noise or any kind of instability, i removed the cap which was soldered at the top of the R14 (close to the uC). The results were almost the same with the cap soldered.

    I got a max-min == 17mV with the min/max being 2.296/2.313V (1mV higher compared to the image below).

    I have already ordered the 3rd set of the pcb having the ldos & the uC/oled display of the device, this time having given higher attention to the grounding.

    The previous 2 pcbs had one single gnd across all layers off course with the layers being connected with lots of vias.

    The last set was done with separate gnds and separate Vin traces.

    I am attaching a screen shot and you could tell me your opinion.

    I am giving you again the rails needed in the entire system.

    There are 2 pcbs that are connected as a sandwich with header pins.

    However gnd is only connected at the lower right corner.

    1) +5.0V exclusively for reed relays

    2) +5.0V exclusively for analog chain opamps (at the second bottom pcb)

    3) +3.3V for the uC of the top pcb

    4) +2.5V & -2.5V exclusively for the analog chain opamps (at the second bottom pcb)

    I won't be publishing too much since this hopefully will reach some point where it can be sold.

    So, this ^ is the top layer. The bottom right corner 5 pins are all gnd for a good connection with the second pcb underneath.

    The header pins on the left side of the gnd header pins are the pos & neg rails needed for the second pcb.

    I have divided the ldos with silkscreen to help better identifying sections.

    You can see that there is a gap that divides the +5V & +3.3V from the analog chain ldos +5V, 2.5V & -2.5V.

    That gap did not exist in the prev versions. The ldos were also not positioned like this in the prev pcb versions.

    This ^ is the layer where the Vin is distributed to each ldo over a different trace as a result of the keep-out areas on the pcb (right side of the pcb).

    The Vin is the right-most header pin of the left pins header at the bottom-right corner.

    The isolated copper section in the center is the 3.3V for the uC + oled display.

    The copper area exactly in the center however (inside the 3.3V copper area) is gnd acting like a farraday cage in conjunction with another layer for ADC inputs.

    I know that not much can be seen here since not all layers are visible.

    That is all i can show you at the moment.

    I liked the idea of me sending a pcb to you for evaluation but let's see how the next set of pcbs will behave and then i could send them over. I am located in Cyprus at the moment.

    Looking forward to your comments, at your convenience.

    Regards

    Manos

  • Hi Stephen,

    The 3rd set of pcbs arrived and i proceeded with the reflow.

    Given that the two previous pcb reflow implementations failed in a way or two, this time i did something different.

    I took a bunch of high power ceramic brick resistors and connected them in series in order to form an area on top of which i placed the pcb after i applied solder paste with the stencil and placed all components.

    I connected the resistors to my bench power supply and eventually adjusted the ps voltage so that the top side (components side) of the pcb stabilized at around 50 deg celcius and left it there for 15 hours.

    That temperature would not harm the components off course since it was much lower than the upper safe temperature limit of operation.

    I took a look at how baking should be done and saw that 24hrs @ 40 deg would be enough to gently push humidity out of the semicons' body without popcorning effects.

    Since my baking took 15hrs @ 50-55 deg i considered this enough for the next step.

    After 15 hrs of baking, i re-adjusted the ps voltage so that the temp of the top side of the pcb was around 100-110 deg celcius and left it there.

    Then, i started using my hot-air gun adjusted at 300 deg on the components until the solder paste liquefied.

    After all components got soldered i placed the pcb away from the high power resistors and left it cool down naturally.

    I did a thorough cleaning because there were a few solder paste micro-ball residue between WSON package pins and also used pure alcohol to clean even more.

    I then applied 5.3V and everything just worked. That was yesterday morning. The pcb has been working since then without any signs of instability.

    One thing that i wanted to say is that in the two previous implementations even the uC made my life miserable because every now and then it would stop working and i had to re-use hot air to melt the solder at its' pins re-do thorough cleaning and then power up again. I thought that i was doing something very wrong and given that i have soldered more than a thousand ICs so far that made me go crazy.

    My conclusion now is rock solid and i will use it to avoid wasting hundreds of euro without any obvious reason.

    It seems that i should have baked the semicons since day one but i did not because i took it for granted that the components shipped inside humidity proof bags are ok to reflow without baking.

    The little papers in those bags were all suggesting that i did not have to bake the parts but that was not the case or that is just my impression.

    Bottom line is that every seems and feels ok now.

    Thanks again for your support.

    Regards

    Manos