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Part Number: LMR16030
I have a question about LMR16030S.
Details are given in the attached document.
Please see my inputs below:
1. Normally frequency is determined by a current, but we have no public data of internal circuit.
2. You can use a 555 circuit to generate the 240kHz signal.
3. Yes, you can if the resistance is resonable.
4. We are not sure about or gaurantee the influence using setups not recommended.
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In reply to Iven Su:
Thank you for your prompt reply.
I'm working with him.
I have any questions.
1.When the operation with the waveform, The LMR16030 switching action could not be synchronized to the external clock of 266kHz. What can be considered as the cause?
2 When TPS54360 which is the pin compatible with LMR16030 was mounted,it was able to be synchronize. Is there any different points in the internal PLL circuit?
3.Please let me know how to calculate switching frequency on this circuit.
In reply to Akinari Takada:
Could you please attach your schematic? What does the sync input signal come from?
As to question 3, the device will work abnormally because PLL circuit doesn't "know" it's Sync mode or RT mode.
Fig.1 shows the circuit diagram when measuring the waveform.
The high level of the SYNC pin is set by a pull-up resistor.
The sync signal is formed by turning TR1 on and off with Signal.
About Question 3;
3.1.Please let me know if the SYNC pin can be held high or low while the LMR16030 is disabled by EN pin.
3.2.Is there a risk of IC failure when the SYNC pin voltage is fixed at 3V or 0V?
3.3.In Fig1, TR1 is turned on when Signal is H level.
If the SYNC pin continues to short, do I need to change the circuit as shown in Fig.2?
Please give me advice.
3.1 Yes, but shutdown current might be higher.
3.2 Yes, there will be a risk if SYNC pin can sink a high current.
3.3 Yes, you need to change to Fig.2.
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