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LP87524B-Q1: How about set ENx PINS

Part Number: LP87524B-Q1

Hello,

Use LP87524B for Radar IC power, during initiate find I2C can't get ACK from LP87524 when ENx is Low.

follow up the below steps, it seems I2C module can't work normal at step 4.

but when pull ENx to high, I2C can work normal.

can you help to check how to configure the ENx statue in initiate process.

The power-up sequence for the LP87524B/J/P-Q1 is as follows:

• VANA (and VIN_Bx) reach minimum recommended level (VVANA > VANAUVLO).

NRST is set to high level (or shorted to VANA). This initiates power-on-reset (POR), OTP reading and

enables the system I/O interface. The I2C host must allow at least 1.2 ms before writing or reading data to the

LP87524B/J/P-Q1.

• Device enters STANDBY-mode.

• The host can change the default register setting by I2C if needed.

• The regulator(s) can be enabled/disabled by ENx pin(s) and by I2C interface

  • Hi Maka Luo,

    Is it possible to get schematics for our review? If yes, you could send it to me tuomo.alatalo@ti.com. Device should give ACK if VANA available and nRST high. If nRST and ENx has been connected together, then behavior is as you describe.

    With Regards

    Tuomo