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TPS65910: PWRHOLD connection

Part Number: TPS65910
Other Parts Discussed in Thread: AM3358, ,

Hi, we are changing the PMIC from TPS65910AA1 to TPS65910A3A1 to support for DDR3 device on an existing product. The PWRHOLD pin was connected to VDDS_DDR(SWIO output) in current product, see below schematic, we realized that the HI level margin become less for the PWRHOLD after the change, as VDDS_DDR from 1.8V to 1.5V. 

We did a experiment on current product that connect the PWRHOLD to the output of VDAC output, but the system cannot power down successfully. Only we change to VAUX33, the system can power off. 

Could you help me to understand the reason of the behavior?

  • PWRHOLD should not be pulled up to the DDR rail.

    If you refer to the TPS65910Ax User's Guide for AM335x Processors User's Guide, it shows that PWRHOLD pin on the PMIC should be wired directly to the PMIC_PWR_EN signal from the processor.

    It is my understanding that PMIC_PWR_EN is a push-pull output and does not require a pull-up resistor. Also, you are showing the resistor (R22) as having 0-Ohm value, which means you are shorting the signal up to the DDR voltage. This may be why the PWRHOLD pin cannot go low.

  • Hi Brian,

    PWRHOLD pull up to DDR rail(VIO output) actually can work on current products, what cannot work is pull up to VDAC output, also pull up to VAUX33 like Starter kit board do also work, so we want to know the reason why connect to VDAC output is not working? From the power OFF sequence in user guide, the VIO, VDAC, VAUX33 drop at same time, I don't see difference among them, then how come it results different power off situation?

    As for the reason we don't connect to processor PMIC_PWR_EN is that we have AM3358 power VDDS_VRTC always provided, so the PMIC_PWR_EN is always ON, this will lead to our system automatically powered up which is not expected design. 

  • YF,

    PWRON, SLEEP, and PWRHOLD input pins on the PMIC work together to determine when the TPS65910 turns on and when it goes to the ACTIVE, SLEEP, or OFF states. By definition, the TPS65910Ax OTP spins for Sitara AM335x do not wait for PWRON pin to start the power-up sequence when VCC7 (VBAT) input power is applied.

    If you look at the TPS65910 datasheet, it says on page 8 that PWRHOLD pin has "Programmable PD (default active)".

    PWRHOLD & GPIO_CKSYNC are both referenced to VDDIO, which is shown on pages 8 & 11 of the datasheet.

    Page 15 of the datasheet shows Digital I/O Voltage Electrical Characteristics. PWRHOLD, GPIO_CKSYNC are listed below:

    • Low-level input voltage, VIL = 0.45V (max)
    • High-level input voltage, VIH = 1.3V (min)

    In your system, VDDIO is connected to VDDA_3P3V. The power source of VDDA_3P3V is not shown in the schematic screen shot you shared,  but the VIL and VIH levels for the PWRHOLD input are constant.

    yf liao said:
    From the power OFF sequence in user guide, the VIO, VDAC, VAUX33 drop at same time

    This is not true. The diagram shows that VIO (VDDS_DDR) and VDAC turn off at the same time, but the diagram does not show VAUX33 turning off. VAUX2 and VAUX33 are the only rails that are not shown turning off at the "Switch-off sequence" timing marker.

    The TPS65910A3EVM-583 shows PWRHOLD can be pulled up to VRRTC to keep the PMIC always enabled. In your design, you need to make sure PWRHOLD <0.45V to be considered logic low and >1.3V to be considered logic high. This is all that matters. 

    When VIO (VDDS_DDR) = 1.8V, it was possible for PWRHOLD to be >1.3V most of the time, but now that VIO = 1.5V it is less likely that PWRHOLD >1.3V and this may be one of the reasons you are seeing a difference in the two boards. They are both wired incorrectly, but on the old board it did not cause a problem.