At low load condition (Vin=3.3V, Vout=1V, Iout only about 100mA) in our circuit the measured Bode Plot phase at 1kHz is at -180 degrees, then rises (!) and crosses zero degrees (!!) at about 22kHz where loop gain still is about 10dB. Unity Gain is at 54kHz, +30 degrees ("Phase margin"). Peak phase of +45° is at 200kHz where loop gain is about -15dB.
This shape of Loop Phase is unexpected and not in line with the simulation result using the TPS50601A-SP_AVG PSpice model
downloaded from the TI website.
Contrary to that weird shape of the Loop Phase, the shape of the Loop gain basically looks healthy; at 5.4kHz, it is about +23dB, and falls very linearly (well, in the log-log bode plot) at 23dB/decade. However, the 0dB point at 54kHz is much higher in frequency compared to simulation, and it is a bit close to the 367kHz switching frequency (fsw).
With "medium" load (Iout about 1A), that strange "rising phase / 0 degree crossing" appearance is gone; the measured loop gain slope is about -30dB/decade around the 0dB point at 29kHz; phase is pretty constant at about +45 degrees above that frequency almost up to 300kHz.
With "high" load (Iout about 2A), the 0dB point is at 23kHz; the shape of gain and phase is almost identical to the "medium" load condition (the loop gain just is some 3dB lower).
This marked dependency of the bode plot on load condition is not in line with the circuit simulation.
We use an LC input filter L=350nH, C=(33uF+0.1ohm)||1uF; output L is 2.2uH, fsw is 367kHz, output C is 330uF.
Time domain 50mA load change from the "low load" condition does show a single 0.6mV regulation loop overshoot (underdamped response, Zout about 0.01 ohms) with about 10us half-width. This measurement also reveals the output capacitor ESR of (also) about 0.01ohm.
In obtaining the Bode plots, the network analyzer output amplitude was set to minimum; a 10dB increase did not cause any significant change in Loop Gain/Phase (aside from noise, which of course increases with decreasing stimulus amplitude).
Q1:
Can you help me understand what that "low load" bode plot phase bahavior is telling me? Could that have to do with the output inductor current ripple "going negative", causing the HI-side FET to briefly in each switch cycle source current into the INPUT filter capacitor in the low-load condition? I can see that this "current reversal" is indeed happening when I measure across the 0.1ohms damping resistor which is in series with the input filter capacitor.
Q2:
What could be the reason for the difference between Bode Plot measurement and simulation?
