LM5050-1-Q1: Maintain external MOSFET off when VS pin is not supplied and VOUT is still present

Hi

I am looking into this and will get back today.

Regards,

Kari.

Hi

When IN is short to GND, OUT is short to GND and Vs is not supplied and connected go GND.

Can you share the if Gate was applied positive and IN was reference for the 5V applied?

Regards,
Kari.

Hello,

I share a picture of VGS. I get the following curve with the configuration suggested by you. 

Don't mind about C2.

C1 is the voltage applied  between GATE and IN. I injected 5V but the voltage is limited to 2V. (Then, it drops to 0V because i switched off the voltage between GATE and IN).

Cordially,

Gowtham

HI

We will need to do verify this in lab and get back as this was not recommended use case.

Need some time here, about 2 days.

Regards,

Kari.

Hi

With all the power removed at the IN , OUT and VS pin: only path from gate to IN is the clamp diode with its cathode in gate and anode in IN pin.

This is shown in datasheet page 12, section 7.2 Functional Block Diagram.

When IN is forced above Gate, the diode conducts and clamps the voltage (5V applied), current will be very high as diode conducts.

This is expected behavior.

Next, with OUT only powered, and no voltage on IN and Vs, MOSFET will remain off.

Regards,

Kari.

Hello,

According to datasheet, the diode clamps at approximately 14V.

In this case,  why does the diode conduct when we applied 5V ?

Cordially 

Gowtham

Hi,

According to datasheet, the diode clamps at approximately 14V.

In this case,  why does the diode conduct when we applied 5V ?

Cordially 

Gowtham

Hi

Clamp diode of 14V is with its anode connected to IC IN pin and clamps diode's connected to IC GATE pin.

14V will be its break down and will not conduct until 14V with Gate pin positive and VIN negative.

If you connect the supply otherway, then this diode will short out the supply and clamp.

Isn't this what is seen in the waveform or my polarity assumption of 5V supply is wrong?

Regards,
Kari.

Hello,

I applied a positive 5V between IC gate pin and IC IN pin so your polarity assumption of 5V supply is wrong.

Cordially

Gowtham

Hi Gowtham,

This is not expected and I need to test this in lab and will need some more time to get back to you.

But i would like to ask why is this a concern when IC is under power down condition.

Regards,
Kari.

Hi Gowtham,

I was able to test this on the EVM today and observe the same.

When the power is off, GATE-IN has a week pull-down about 50ohm causing this.

Note this is not intended use case when power is off we expect gate also to be off, that is gate is pulled to IN, and this is not incorrect operation.

Can you please help to understand your concerns from a application or system perspective if the gate is pulled IN and its impact?

Regards,

Kari.

Hello,

In our company, we used to discharge CISS of MOSFET by a 100k resistor parallel to gate source of MOS.

However when we placed this resistor with this application, the IC didn't regulate VDS to 22mV.

So we want to ensure that the function pull down Gate Source of MOS is present (consequently VGS is at 0V) when the power supply of IC (VS pin) is off . 

Cordially 

Gowtham