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LM5104: When VDD = 0, are the HO and LO outputs in guaranteed states to have both MOSFETs turned off?

Part Number: LM5104

Hi,

In case the supply voltage VDD = 0, are the HO and LO outputs of LM5104 in guaranteed states to have both MOSFETs turned off?

Thanks!

Marcus

  • Hi Marcus, 

    Thanks for your help promoting our drivers. 

    Please refer to section 7.3.2 of the datasheet referencing the UVLO feature of the IC which holds the OUT pins low until sufficient bias to drive the power FETs. 

    "When the supply voltage is applied to VDD pin of LM5104, the top and bottom gates are held low until VDD exceeds UVLO threshold, typically about 6.9 V. Any UVLO condition on the bootstrap capacitor will disable only the high-side output (HO)"

    I will reach out to you shortly to further discuss this opportunity.

    Meanwhile, please let us know if you have additional questions.

    Regards,

    -Mamadou

  • Thank you Mamadou!

    What happens if there is no / not sufficient supply voltage applied to VDD (e.g. VDD = 0V ... 6V)? Is it possible, that the connected Mosfets might not be fully switched off during that condition?

    Best regards,

    Marcus

  • Hi, Marcus,

    Our office is closed for the holidays.

    My colleague should get back to you by Jan 6th. If you don't hear from him by then, or need an earlier answer, let me know.

  • Hello Marcus,

    There is internal logic that drives the driver output to ground when the VDD UVLO is below the turn on thresholds as VDD is rising.

    The driver outputs can be actively driven low when VDD has ~1.2V and above on VDD, or HB-HS.

    Confirm if this addresses your question, or you can post additional questions on this thread.

    Regards,