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TPS7A8300: Output cap value

Expert 1545 points
Part Number: TPS7A8300
Other Parts Discussed in Thread: TPS7A83A

Hello 

The TPS7A8300 is one of our favorite LDO's due to the combination of good PSRR, low noise and small drop out voltage all together with a small package and good thermal performance. 

However lately we see an increased demand from customers for a very small products, especially on the height. This leads to my question about the LDO's output capacitor selection:

The datasheet recommends 22uF cermaic cap as a minimum. The shortest 22uF cap I have found is 1.6mm. I need the cap to be 1mm max. For this reason I would like to use 2 or 3 GRM188Z71A106KA73D in parallel. The output voltage is typically 3.3,1.8,1.2,0.9 V (mostly used to power TI DAC's)

Note: due to the temp. of the system, we use only X7R or higher type. 

Can you please advise about the LDO performance with those output capacitors? are 2 enough or we need 3? Can you simulate this? 

Thanks

  • HI Izik,

    Thank you and glad you like the TPS7A83.

    There is nothing wrong with using smaller capacitors in parallel to allow for lower Z-height components while still meeting the minimum capacitance guidelines. I would plan your board for 3 in parallel and if your testing suggests you can remove one, then you can do that at a later time. 

    Note: for stability, when we simulate we use the minimum ESR value as simulating the capacitor dynamics along with the LDO performance would take quite some time. 

    I hope this helps.

  • Many thanks for you (very) fast response. 

    When the datasheet recommends on a 22uF capacitor, it is clear that the LDO will see a lower value depending on the DC bias and temperature and the type of capacitor selected. 

    Could you please advise what is the minimum capacitance required (calculated after the DC bias and temperature capacitance decrease) for a correct operation of the LDO?

    What is the minimum ESR in order to assure stability? 

    Thanks again

    Izik

  • HI Izik,

    The TPS7A83A datasheet is a bit clearer on the output capacitance:

    The difference between these two parts is the sequences of VBIAS, EN, and VIN. The non-A version has a dependance, the A version does not. 

    Here it recommends 10uF capacitance assuming a ceramic capacitor.

    During our simulations, we would have assumed a minimum ESR of ~5mOhm. Your layout will have an impact on the effective ESR which is why I recommend putting pads for at least 3 of these on the board. If you would like, we can send you an EVM to try it out with your specific load conditions. 

    I hope this helps.

  • Hi

    Please see the ESR plot of the capacitor I want to use. 

    At 1MHz the ESR is 4mOhm, and if I use 3 caps in parallel I'll get 1.33mOhm, less than the minimum. Does the ESR in 1MHz frequency may cause in-stability? 

    In addition, I will connect the caps on the other side of the board, so there will be a through hole via (the board is 1.2mm thick) which may add some parasitic inductance before the capacitor. The via will be placed directly after the output pin of the LDO so the trace length other than the via is minimal (~10mils). Do you think it may affect the performance? 

    Thanks 

    Izik

  • HI Izik,

    I was able to confirm that the simulations for this device assumed an ideal capacitor (i.e. 0 impedance). So long as you maintain the 10uF of total capacitance, the device will be stable.

    Having a solid layout like it seems you are already planning only helps to ensure that.

    Regards,