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LM1085: Parallel LDO design possible?

Intellectual 470 points

Replies: 6

Views: 161

Part Number: LM1085

Hello,

I'm trying to convert 20V/5A SMPS power to 18~19V for my noise sensitive application. I couldn't find a good buck converter for my design.

I came across High-Current Low-Noise Parallel LDO Reference Design (http://www.ti.com/tool/TIDA-01232 ) and I want to implement this concept to my design.

Due to thermal issues, I'm planning to split the currents to 3 LDOs and have around 2A load per LDO.

1. Can the circuit below work?

2. From the design document, I need to add a Ballast resistor and if I add the Ballast resistor like the figure 1 below, can I use a ceramic capacitor instead of Tantalum or aluminum?

3. If LM1085 can't be used for my application, is there a good alternative of LM1085?

I'm willing to  spend up to $6 just for the LDOs ($1.5(@4ku) x 4ea or $2(@3ku) x 3ea)

20V w/ tolerance input and 18V/5.5A output needs be supported.

Figure 1.

  • Hi Brian, 

    I am currently looking into your question, please allow 2 business days for me to get you the reply. 

    Regards, 
    Jason Song

    Please click the "Resolved" link at the bottom of this post if I have answered your question.

  • In reply to Jason Song:

    Hello Jason,

    Thanks for looking into my question.

    Please let me know if you need any other information for my design.

    Regards,

    Brian

  • In reply to Brian Han1:

    Hi Brian, 

    Technically you could parallel any LDO and boost the maximum total output current by splitting the current between different LDOs. In a real application, however, the tricky part is on how to choose the Rblast value to minimize the current drop while still maintaining the current balance between the LDOs. 

    There is another discussion on this topic on E2E that I find helpful for any parallel application consideration. I would recommend going through this post and calculate the Rblast at your conditions. 

    https://e2e.ti.com/support/power-management/f/196/t/832277

    For LM1085-ADJ, the output itself can give 2% accuracy but you will also need to consider the error term created by the resistor dividers. A 2% output accuracy may not give you a practical value for Rblast, in order to make reduce the Rblast, you may need to measure the actual output voltage difference at the conditions you are interested in and use the measured Evout in the equation. 

    A better option would be TPS7A47, but the issue is that one TPS7A47 can only output 1A of current. Let me know what you think and we'll go from there. 

    Regards, 
    Jason Song

    Please click the "Resolved" link at the bottom of this post if I have answered your question.

  • In reply to Jason Song:

    Hello Jason,

    I have read the linked post and looked into TPS7A47 and the syncing NR/SS pins seem to help to minimize the Vout tolerance.
    The only problem is the price. I need to sink 5.5A @ 19V then I need 6 TPS7A47, which is almost $14 from the supplier.


    Is there a way to tighten the Vout tolerance with other passive components?
    The only thing that I could think of is the feedforward capacitor that could help the stability, but not sure if it can help accuracy.
    Also, I will be using 0.1% resistors if that helps.


    Because I'm going from 20V to ~19V, there is not a big gap in efficiency compared to buck converter and I think I can sacrifice a few mA to apply this design.
    Is there a rule of thumb how much current drop is allowed in a parallel LDO setup?


    Regards

    Brian

  • In reply to Brian Han1:

    Hi Brian, 


    Is there a way to tighten the Vout tolerance with other passive components?

    --If you use the same passive components and do a matching layout, you should achieve better output accuracy. 


    The only thing that I could think of is the feedforward capacitor that could help the stability, but not sure if it can help accuracy.
    Also, I will be using 0.1% resistors if that helps.

    -The feedforward only helps with AC performance. The 0.1% resistor will help with the DC output accuracy. 

    Is there a rule of thumb how much current drop is allowed in a parallel LDO setup?

    -The allowed current drop is decided by your application. For example, you need 19V output with +/-3% tolerance, your maximum allowed current drop would be 3% below 19V. 

    LM1085 may work for your application, however, you will need to characterize the output difference between the LDOs. The total 2% accuracy listed in the datasheet normally includes lot-to-lot variation, temperature, and load variations. For a specific application case, you are likely to see tighter accuracy, and with this, you could reduce the size of the Rblast. Also for the Rblast, you could use PCB traces to achieve the Rblast. For some up-coming devices, we will have NR to Output accuracy spec in the datasheet that will help a lot to reduce the size of the Rblast. Unfortunately, for LM1085 you will need to get accurate data for your application. 

    Regards, 

    Jason Song

    Please click the "Resolved" link at the bottom of this post if I have answered your question.

  • In reply to Jason Song:

    Hi Jason,

    Since there are not many options available, I will have to work as I go with LM1085.

    Thanks so much for your help.

    Regards

    Brian

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