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TPS3850: About Latch Circuit

Onur Keskin
Intellectual 390 points
Part Number: TPS3850

Hi,

I am sharing my schematic. I will use 5V for supply. But the supply of buffer IC is 3V3. Does this setup cause problems?

  • 0
    TI__Genius 12630 points

    Onur,

    This should not cause any problem. The reason is that the CRST internal voltage reference is 1.21V meaning a 3.3V will still be considered logic high on CRST even if the TPS3850 VDD is 5V. The circuit will operate correctly if the buffer can output greater that 1.21V at the output. Please be sure to test your circuit and let me know if you have any additional questions. Thanks!

  • 0 in reply to Michael_DeSando
    Intellectual 390 points

    Thanks Michael,

    I have one more question. The maximum capacity value in "Latching a Watchdog Timer" document is 5nF. I will use 4.7nF tol ±10%.  Do I need to change the capacitor value?

    4.7nF is a capacity I use frequently. So I didn't choose a smaller value. But if necessary, I wil change it.

  • 0 in reply to Onur Keskin
    TI__Genius 12630 points

    Onur,

    Yes this is not an issue. The 5nF will add a very small additional delay before the /RESET or /WDO comes back to logic high if the latch is removed so that is why we recommend a low value. But there is no impact on the latch functionality, just when the latch is removed if it is removed. If the buffer is removed, the capacitor on CRST then sets the "Reset time delay". If you wish to increase the reset time delay for when the latch is removed, you can increase the capacitor on CRST. Refer to section 8.1.1 in the datasheet to understand the relationship between the capacitor value and the reset delay.

  • 0 in reply to Michael_DeSando
    Intellectual 390 points

    Michael ,

    Thank you for your reply.