CSD16325Q5: CSD16325Q5

Hi Santosh,

Thanks for your interest in TI FETs. Below you will find a link for how TI specifies SOA in our MOSFET datasheets. The SOA curves included in the CSD16325Q5 datasheet are for a single on pulse. For repetitive pulses, you can use the transient thermal impedance curves included in the MOSFET datasheet. The CSD16325Q5 is an older device and the SOA curves are calculated. For pulse widths < 1ms, the maximum current is limited by the absolute maximum current ratings (200A) on page 1 of the datasheet. Because this is an older device, we recommend the CSD17573Q5B as a newer replacement. This SOA curves in the datasheet for this device are based on actual test-to-failure data.

Hi Santosh,

The continuous drain current ratings on page 1 of the MOSFET datasheet are calculated quantities except for the package limited current which is determined by the interface between the silicon die and package/lead frame. This can either be bond wires or copper clip which the CSD17573Q5B uses. I've included some links below that explain continuous current ratings, thermal impedance and power dissipation capability by package for TI FETs. Your calculation is correct. However, achieving RthetaJA of 2degC/W is going to be very difficult if not impossible to implement. TI specs RthetaJC to the thermal pad on the bottom of the package at 0.8degC/W max. Dissipating 43W continuously in a 5x6mm SON package is not practical. If this is pulsed, you can use the transient thermal impedance curves in the MOSFET datasheet to calculate the junction temperature rise. You may want to consider paralleling multiple FETs to spread the heat over a larger surface area and number of packages.

Hi Santosh,

In theory, you can use the same calculation to determine the max continuous current at VDS = 1V as follows:

PDmax = (Tj - Tcase)/RthetaJC, IDmax = PDmax/VDS

For Tj = 130degC & Tcase = 75degC, PDmax = (130-75)/0.8 = 68.75W & IDmax = 68.75W/1V = 68.75A.

In reality, you would need a heatsink and thermal interface that can dissipate 68.75W to ambient. If the ambient temperature is 25degC, then the required thermal impedance of the heatsink + thermal interface can be calculated as follows:

RthetaCA = (75degC - 25degC)/68.75W = 0.727degC/W which is not very realistic for a SMT package where the main path for heat removal is into the PCB. You can heatsink the top of this package but RthetaJC to the top case is about 11degC/W. You can also heatsink the backside of the board. Without a heatsink, I have seen a good PCB design be able to achieve 20 - 25degC/W effective RthetaJA. Then the calculation becomes:

PDmax = (Tj - Ta)/RthetaJA_eff = (130-25)/25 = 4.2W.

At Ta = 55degC, this is reduced to 3W (IDmax = 3A at VDS = 1V).

TI discontinued their dual-cool MOSFET packaged products with exposed metal on the top of a SON package. The only package TI offers that can be attached directly to a heatsink is the TO220. Below is a link to a listing of all TI FETs in TO220 package. RthetaJC for this package is 0.4degC/W max. There are many heatsink manufacturers that can help you with heatsink design and selection.

Hello Santosh,

Thanks again for your interest in TI MOSFETs. Please see my answers below:

1. Results from thermal simulations done by TI packaging team.
2. The CSD17573Q5B and CSD16325Q5 are both copper clip packages. Instead of bond wires, the connection to the FET source uses a copper clip. 100A of current may not immediately melt or damage the copper clip but is the maximum current based on current density limitations.
3. 400A is the maximum limit of TI's test equipment. IDM is a calculated value that uses the transient thermal impedance (Figure 1 in the datasheet) and assumes the case temperature is held at 25degC: PDM = (Tjmax - Tcase)/ZthetaJC & IDM = sqrt(PDM/rds_on), where the value for rds_on is at Tj = 150degC (about 1.7x the value at 25degC - see Figure 8 in the datasheet). Our calculation comes out to ~485A which is truncated down to 400A. Please check link to blog below.
4. TI does not specify, test or guarantee rds(on) at VGS = 2.5V. The rds(on) vs. VGS curves included in the datasheet are for a typical device. VGS = 2.5V is on the very steep part of the curve where rds(on) increases exponentially. A slight shift in threshold voltage due to process variation can result in a large change in rds(on).

Hello Santosh,

I reviewed the IDM calculations for the CSD17578Q5B from the original characterization data. Below is how we arrived at 485A:

• For 1% duty-cycle and 0.01s pulse width: normalizing factory = 0.375 (measured data)
• PDM = (150C - 25C) / (0.8C/W x 0.375) = 417W
• At 150C, rds(on) = 1.77mOhm (measured data)
• IDM = sqrt(417W / 1.77mOhm) = 485A

Now, I know the datasheet says that IDM is with pulse duration <= 100us and duty cycle <= 1%. I'm not certain why this calculation used ZthetaJC at 10ms pulse duration, 1% duty cycle. Obviously, the current would be much higher using ZthetaJC for 100us, 1% duty cycle. In any case, we truncate the value to 400A because that is the maximum current of our test equipment.

I'm not sure what you mean by VDD. Should this be VDS, drain-source voltage of the FET? There is not a limitation on VDS to get 40A IDS. Please look at Figures 2 & 3 in the datasheet. With the right gate drive, you should easily achieve IDS = 40A at VDS = 0.8V. The typical data shows you will need VGS ~ 2.45 V to get IDS = 40A.

Hello Santosh,

As it has been explained to me, the 400A cutoff for IDM is a limitation of the equipment used to test TI FETs. I do not have any further details on this topic. TI tests rds(on) at the conditions specified in the Electrical Characteristics table in the MOSFET datasheet. The duration of the current pulse is very short (< 1ms) to avoid self-heating which would yield a higher value for rds(on) due to the positive temperature coefficient of that parameter. I am not at liberty to share any more information about TI's production test procedures.