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BQ25883: I2C time sequence requirement

Part Number: BQ25883

Hi team,

When customer looks into BQ25883 datasheet EC table, for the I2C interface section, has the questions about requirement of  sequence: The hold time of SDA should be less than 70ns, and the rise and fall time should be greater than 10ns. Under normal circumstances, a larger hold time is better. The minimum rise and fall time is usually not required, but BQ25883 datasheet seems to be different from the general requirements.

Could you please clarify whether these three values are correct?

Best Regards,

Gene

  • Dear Gene,

    These values are indeed correct.

    Thanks,

    Mike Emanuel

    Please click "This resolved my issue" button if this post answers your question.

  • Hi Mike

    Thank you for checking, actually customer test BQ25883 I2C timing data as below, it works fine but have concern since not match our datasheet. So want to double check with team if there are actions need to be taken:

    Fig1 Thd_dat, data hold time,  measured about 350ns, as shown in Fig1. But datasheet required 0-70ns

    Fig2  The fall time of SDA,trDA, is less than 1ns,If  need to reach more than 10ns as datasheet recommended, they need to parallel 200pf capacitor on the SDA to make the edge very slow. But it seems to be weird

  • Gene,

    Can you please provide a schematic showing how the I2C is connected in relation to the charger? In addition can you please identify in the figures which traces are which?

    Thanks,

    Mike Emanuel

  • Hi Mike:

    1, the following picture shows the schematics, the testpoints are I2C_CLK and I2C_SDA.

    2, and the following picture shows the falling time of SDA signal:

    3, the following picture shows the timing of I2C signals: the yellow one is SDA signal and the purple one is CLK signal.

  • Hi Mike:

    1, the following picture shows the schematics, the testpoints are I2C_CLK and I2C_SDA.

    2.and the following picture shows the falling time of SDA signal:

    3.the following picture shows the timing of I2C signals: the yellow one is SDA signal and the purple one is CLK signal.

    Best Regards,

    Gene

  • Dear Gene,

    According to the I2C specification, the Hold Time t_HD,STA is the minimum amount of time the data should be low before SCL goes low. It appears in your waveform that your SCL is going low before SDA. I am wondering if the wrong event is being measured. Can you please confirm this?

    For the fall time, it looks as if the edge is being captured on a wider scale and then being zoomed in. I can almost see the individual points of the trace. Can you trigger off of a smaller time scale to better capture the data?

    In addition, how are you deciding the thresholds to measure the fall time? The standard says 70% to 30% of full amplitude. I am having trouble determining your full amplitude from the image quality. Can you confirm your pullup rail?

    I am also concerned that your data line drops below ground and that this could be affecting your measurement. Is there anything else connected to your I2C which could be pulling your SDA below ground?

    Thanks,

    Mike Emanuel

    Please click "This resolved my issue" button if this post answers your question.

  • Hi Mike:

    Thanks for your feedbacks.

    We found that the timing requirements from BQ25883 datasheet were the same as I2C high speed criteria(3.4MHz), but we only used 100KHz as communication speed, and if comparing to the criteria of 100KHz, we can meet its timing requirements.

  • Glad I could help!

    If your question was answered, please click "This resolved my issue."

    Thanks,

    Mike Emanuel