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ucd3138 PSFB Filter's Calculation cycle

Prodigy 190 points

Replies: 3

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Hello.

I am currently testing with the ucd3138 psfb sample program.


We are currently investigating Filter and want to know the calculation cycle of Ki.

It is stated in the manual that the sampling period of the deviation Xn (EADC) is 8MHz or 16MHz, but I want to know how fast the value is accumulated in the integrator.

  • The filter takes about 500 nanoseconds to run.  This is for a simple single sample per filter run.  If you request various types of sample averaging, the time will take longer.  

    Happy Debugging,

    Ian Bower

  • In reply to Ian Bower:

    Thank you for a quick reply.

    One more thing I want to ask.
    I want to know the operation cycle of Yn for PID control.
    This is the period from when Xn is captured to when Yn is output.
    best regards.
  • In reply to user5952333:

    The number I already gave you is for that.  Let me give you the whole timing sequence.

    1. Sequence is started by sample trigger to front end, typically from a DPWM

    2. The next EADC sample after the sample trigger is used to start the filter. The EADC sample is taken every 128 or 64 nanoseconds.  The EADC runs asychronously to the sample trigger, because the EADC cannot be stopped and started, it has to run continuously.  So if the EADC is set for 64 nanosecond conversion time, this could take from 64 to almost 128 nanoseconds

    3. This is the filter, about 500 nanoseconds.

    4. Next the filter output is latched into the DPWM logic.  We strongly recommend that you set the DPWM up so that this is latched at the end of the period.  Otherwise there is an increased risk of long pulses and shootthrough, depending on DPWM setup and topology.  

    Happy Debugging,

    Ian Bower

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