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TPS65132: ENP and ENN pull low cause registers reset to NVM

Part Number: TPS65132

Hi Team,

My customer says that they initially sets VOUT to 5.5V vias register,  but when they pull the ENP and ENN to 0. Then pull it to 1 again, the VOUT resets to 5V. The customer gets two questions:

1. How to reset register's value to default on-the-fly?

2.If EN cycle if reset register's value?

-Wenhao

  • Hi Wenhao,

    Thanks for your question. Let me contact the expert for this part. You can expect a response by 3/16/20.

    Best,

    Grant

  • Hi Grant,

    Any updates to this issue?

    -Wenhao

  • Hi Wenhao,

    It looks like the thread assignment didn't go through. My apologies. I will verify the expert knows about your question.

    Best,

    Grant

  • Hello Wenhao,

    When both ENN and ENP are low, device resets to default settings stored in the eeprom. Customer can store the desired values of a specific application to EEPROM by first updating the register content to desired values and then setting WED (Write EEPROM data) bit to 1. I am copying below the relevant excerpt from the datasheet.

    ========

    Write description: The user has to program all Registers first (0×00 to 0×03), then set the WED (Write EEPROM Data) bit to 1. A dead time of 50 ms is then initiated during which the register content or all registers (0×00 ~ 0×03) are stored into the non-volatile EEPROM cells. During that time, there should be no data flowing through the I 2C because the I 2C interface is momentarily not responding. After the 50 ms have passed, the WED bit is automatically reset to 0, and the user is able to read the values or program again.

    ======

    Kind Regards,

    Liaqat