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  • TI Thinks Resolved

UCD3138: UCD3138: 2P interleaved forward with average current mode control

Prodigy 110 points

Replies: 7

Views: 69

Part Number: UCD3138

Hi Experts,

I want to implement 2P interleaved forward that uses two control loops, Voltage and Current.

But there isn't a lot of documentation on using average current mode control. Is there any further documentation or firmware with average current mode using the UCD3138?

I use this firmware to implement voltage mode control.

https://e2e.ti.com/support/power-management/f/196/t/844177?tisearch=e2e-sitesearch&keymatch=UCD3138%20Forward

Thanks!

  • Hi Tina,

    We do not have specific documentation or code of average current mode ITTF.

    But I can guide you on how to configure and interconnect the two loops to achieve average current mode.

    The top level idea is pretty simple, the voltage loop will not connect to DPWMs.

    The output of voltage loop filter will be connected to the DAC (reference) of the average current loop's front end.

    The average current loop that is connected to average current signal will drive a separate filter that it's output will drive the DPWMs.

    I am composing the details and will post more information by tomorrow.

    Regards,

    Yitzhak

    Yitzhak Bolurian

  • In reply to Yitzhak Bolurian:

    Tina, the LLC EVM doesn't have the right topology, but it does to average current mode control.  

    The description is here:

    http://www.ti.com/tool/UCD3138ALLCEVM150

    Happy Debugging,

    Ian Bower

  • In reply to Ian Bower:

    Thanks to Yitzhak for pointing out my mistake, average current mode control is actually shown in the HSFB firmare here:

    http://www.ti.com/tool/UCD3138HSFBEVM-029

    That's probably better anyway, because the setup on the DPWMs is closer to what you want - there's a pulse width, rather than a resonant frequency.  

    Happy Debugging,

    Ian Bower

  • In reply to Yitzhak Bolurian:

    Hi Yitzhak,

    Thank you for reply.

    Please offer more information how to configure and interconnect the two loops to achieve average current mode.

    Thanks!

  • In reply to Ian Bower:

    Hi Ian,

    Thank you for reply.

    I can study the HSFB firmware first.

  • In reply to Yitzhak Bolurian:

    Hi Yitzhak,

    Can you offer more details how to configure and interconnect the two loops to achieve average current mode?

    Thanks!

  • In reply to Tina hsieh:

    Hi Tina,

    Here is the example code.

    Look at the #else section:

    void init_loop_mux(void)

    {

    #ifdef voltage_mode_control //voltage mode control

    //Rail 1 Interconnects

    LoopMuxRegs.FILTERMUX.bit.FILTER0_FE_SEL = 0; // connect filter 0 to front end 0.

    LoopMuxRegs.FILTERMUX.bit.FILTER0_PER_SEL = 0; // Selects source of switching cycle period for Filter 0 Module

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM0_EN = 1; // Enables Sample Trigger from DPWM 0 to Front End Control 0

    LoopMuxRegs.DPWMMUX.bit.DPWM0_FILTER_SEL = 0; // filter0 is providing duty input to this DPWM

    LoopMuxRegs.DPWMMUX.bit.DPWM1_FILTER_SEL = 0; // filter0 is providing duty input to this DPWM

    #else

    LoopMuxRegs.FILTERMUX.bit.FILTER0_FE_SEL = 0; // connect filter 0 to front end 0.

    LoopMuxRegs.FILTERMUX.bit.FILTER0_PER_SEL = 0; // Selects source of switching cycle period for Filter 0 Module

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE0_TRIG_DPWM0_EN = 1; // Enables Sample Trigger from DPWM 0 to Front End Control 0

    LoopMuxRegs.FILTERMUX.bit.FILTER1_FE_SEL = 1; // connect filter 0 to front end 0.

    LoopMuxRegs.FILTERMUX.bit.FILTER1_PER_SEL = 0; // Selects source of switching cycle period for Filter 0 Module

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE1_TRIG_DPWM1_EN = 1; // Enables Sample Trigger from DPWM 0 to Front End Control 0

    LoopMuxRegs.EXTDACCTRL.bit.EXT_DAC1_EN = 1; // average current mode

    LoopMuxRegs.EXTDACCTRL.bit.DAC1_SEL = 4; //DAC2 select filter 0 output

    LoopMuxRegs.DPWMMUX.bit.DPWM0_FILTER_SEL = 1; // filter1 is providing duty input to this DPWM

    #endif

    //Rail 2 Interconnects

    #ifdef voltage_mode_control

    LoopMuxRegs.FILTERMUX.bit.FILTER1_FE_SEL = 1; // connect filter 1 to front end 1.

    LoopMuxRegs.FILTERMUX.bit.FILTER1_PER_SEL = 2; // Selects source of switching cycle period for Filter 1 Module

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE1_TRIG_DPWM2_EN = 1; // Enables Sample Trigger from DPWM 2 to Front End Control 1

    LoopMuxRegs.DPWMMUX.bit.DPWM2_FILTER_SEL = 1; // filter1 is providing duty input to this DPWM

    LoopMuxRegs.DPWMMUX.bit.DPWM3_FILTER_SEL = 1; // filter1 is providing duty input to this DPWM

    #endif

    // Configure frame sync and sample trigger.

    LoopMuxRegs.FECTRL0MUX.bit.DPWM0_FRAME_SYNC_EN = 1; // Enables DPWM Trigger from DPWM0 Frame Sync to Front End 0 Control

    LoopMuxRegs.FECTRL1MUX.bit.DPWM2_FRAME_SYNC_EN = 1; // Enables DPWM Trigger from DPWM2 Frame Sync to Front End 1 Control

    LoopMuxRegs.FECTRL2MUX.bit.DPWM1_FRAME_SYNC_EN = 1; // Enables DPWM Trigger from DPWM2 Frame Sync to Front End 1 Control

     

    //Master and Slave set-up

    LoopMuxRegs.DPWMMUX.bit.DPWM0_SYNC_SEL = 0; // DPWM0 is a Master

    LoopMuxRegs.DPWMMUX.bit.DPWM1_SYNC_SEL = 0; // DPWM1 is a Slave, sync with DPWM0

    LoopMuxRegs.DPWMMUX.bit.DPWM2_SYNC_SEL = 2; // DPWM2 is a master

    LoopMuxRegs.DPWMMUX.bit.DPWM3_SYNC_SEL = 2; // DPWM3 is a Slave, sync with DPWM2

    #ifdef voltage_mode_control

    // Feed Forward Configuration

    LoopMuxRegs.FILTERMUX.bit.FILTER2_FE_SEL = 2; // connect filter 2 to front end 2

    //Connections to the outputs of the filters handled in the FF state

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE2_TRIG_DPWM0_EN = 1; // Enables Sample Trigger from DPWM 0 to Front End Control 2

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE2_TRIG_DPWM2_EN = 1;

    //Probably Don't need; keep - Verify - Keep/delete

    //LoopMuxRegs.FECTRL2MUX.bit.DPWM1_FRAME_SYNC_EN = 1; // Enables DPWM Trigger from DPWM1 Frame Sync to Front End Control 2 : For Ramp

    }

    #else

    LoopMuxRegs.FILTERMUX.bit.FILTER2_FE_SEL = 2; // connect filter 2 to front end 2.

    LoopMuxRegs.FILTERMUX.bit.FILTER2_PER_SEL = 1; // Selects source of switching cycle period for Filter 2 Module

    LoopMuxRegs.SAMPTRIGCTRL.bit.FE2_TRIG_DPWM1_EN = 1; // Enables Sample Trigger from DPWM 1 to Front End Control 2

     

    LoopMuxRegs.EXTDACCTRL.bit.EXT_DAC2_EN = 1; // average current mode

    LoopMuxRegs.EXTDACCTRL.bit.DAC2_SEL = 4; //DAC2 select filter 0 output

    LoopMuxRegs.DPWMMUX.bit.DPWM1_FILTER_SEL = 2; // filter2 is providing duty input to this DPWM1

    #endif

    }

     

    void init_front_end0(void)

    {

    FeCtrl0Regs.EADCCTRL.bit.AFE_GAIN = 3; // Gain 0|1x 1|2x 2|4x 3|8x

    FeCtrl0Regs.EADCCTRL.bit.EADC_MODE = 0; //'0':Standard Mode - Triggers on DPWM;"1":averaging mode.

    FeCtrl0Regs.RAMPCTRL.bit.RAMP_EN = 1; //Enable Ramp module use

    FeCtrl0Regs.EADCCTRL.bit.SAMP_TRIG_SCALE = 0; //# of samples between conversions [0 = every sample, 1 = every 2 samples, etc] to 15

    FeCtrl0Regs.EADCCTRL.bit.EADC_ENA = 1; //Turns the EADC on

    FeCtrl0Regs.EADCCTRL.bit.AVG_MODE_SEL = 1; // Averaging 0|2x 1|4x 2|8x;

    FeCtrl0Regs.EADCCTRL.bit.AVG_SPATIAL_EN = 1; //ENABLE averaging;

    }

    #ifdef voltage_mode_control //voltage mode control

    void init_front_end1(void)

    {

    FeCtrl1Regs.EADCCTRL.bit.AFE_GAIN = 3; // Gain 0|1x 1|2x 2|4x 3|8x

    FeCtrl1Regs.EADCCTRL.bit.EADC_MODE = 1; //'0':Standard Mode - Triggers on DPWM;"1":averaging mode.

    FeCtrl1Regs.RAMPCTRL.bit.RAMP_EN = 1; //Enable Ramp module use

    FeCtrl1Regs.EADCCTRL.bit.SAMP_TRIG_SCALE = 0; //# of samples between conversions [0 = every sample, 1 = every 2 samples, etc] to 15

    FeCtrl1Regs.EADCCTRL.bit.EADC_ENA = 1; //Turns the EADC on

    FeCtrl1Regs.EADCCTRL.bit.AVG_MODE_SEL = 2; // Averaging 0|2x 1|4x 2|8x;

    FeCtrl1Regs.EADCCTRL.bit.AVG_SPATIAL_EN = 1; //ENABLE averaging;

    }

    #else

    void init_front_end1(void)

    {

    FeCtrl1Regs.EADCCTRL.bit.AFE_GAIN = 2; // Gain 0|1x 1|2x 2|4x 3|8x

    FeCtrl1Regs.EADCCTRL.bit.EADC_MODE = 0; // Continuous error mode, no average

    FeCtrl1Regs.RAMPCTRL.bit.RAMP_EN = 0; // Enable Ramp module use

    FeCtrl1Regs.EADCCTRL.bit.SAMP_TRIG_SCALE = 0; // # of samples between conversions [0 = every sample, 1 = every 2 samples, etc] to 15

    FeCtrl1Regs.EADCCTRL.bit.EADC_ENA = 1; // Turns the EADCon

    FeCtrl1Regs.EADCCTRL.bit.AVG_MODE_SEL = 1; // Averaging 0|2x 1|4x 2|8x

    FeCtrl1Regs.EADCCTRL.bit.AVG_SPATIAL_EN = 1; //ENABLE averaging;

    }

    #endif

    #ifdef voltage_mode_control //voltage mode control

    void init_front_end2(void)

    {

    FeCtrl2Regs.EADCCTRL.bit.AFE_GAIN = 0; // Gain 0|1x 1|2x 2|4x 3|8x

    FeCtrl2Regs.EADCCTRL.bit.EADC_MODE = 0; // Continuous error mode

    FeCtrl2Regs.RAMPCTRL.bit.RAMP_EN = 1; // Enable Ramp module use

    FeCtrl2Regs.EADCCTRL.bit.SAMP_TRIG_SCALE = 0; // # of samples between conversions [0 = every sample, 1 = every 2 samples, etc] to 15

    FeCtrl2Regs.EADCCTRL.bit.EADC_ENA = 1; // Turns the EADCon

    FeCtrl2Regs.EADCCTRL.bit.AVG_MODE_SEL = 2; // Averaging 0|2x 1|4x 2|8x

    }

    #else

    void init_front_end2(void)

    {

    FeCtrl2Regs.EADCCTRL.bit.AFE_GAIN = 2; // Gain 0|1x 1|2x 2|4x 3|8x

    FeCtrl2Regs.EADCCTRL.bit.EADC_MODE = 0; // Continuous error mode, no average

    FeCtrl2Regs.RAMPCTRL.bit.RAMP_EN = 0; // Enable Ramp module use

    FeCtrl2Regs.EADCCTRL.bit.SAMP_TRIG_SCALE = 0; // # of samples between conversions [0 = every sample, 1 = every 2 samples, etc] to 15

    FeCtrl2Regs.EADCCTRL.bit.EADC_ENA = 1; // Turns the EADCon

    FeCtrl2Regs.EADCCTRL.bit.AVG_MODE_SEL = 1; // Averaging 0|2x 1|4x 2|8x

    FeCtrl2Regs.EADCCTRL.bit.AVG_SPATIAL_EN = 1; //ENABLE averaging;

    }

    #endif

    Hope this helps,

    Regards,

    Yitzhak Bolurian

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