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ISO5452: ISO5452

Richard Cummaro
Prodigy 40 points
Part Number: ISO5452

Gentlemen,

I'm working on a three level Neutral point clamp (NPC) inverter for a motor drive and using the ISO5452 driver chip. The inverter is comprised of  SiC mosfets/diodes.

I seem to be getting an erroneous DSAT trip when I reach a certain output current level. The DSAT trip occurs when Q1( the top transistor in a phase leg) turns off. The DSAT sense voltage begins to rise as it takes time for the DSAT diodes (connected to the drain of the mosfet) to block the voltage (Trr is rated at 75ns). The voltage does spike quite high during this time (20-25V) and apparently trips the chip off. Seems to be a function of the load current. Maybe since this voltage exceeds the Vdd voltage (19) this is also causing a problem?

I've tried to clamp this voltage with a 12V zener as shown in the app note ISO5452tiduc70a. That did not work. Maybe the zener is too slow.

I've also tried tying the RST pin to IN+ for an auto reset that would keep the chip in reset during the off time as suggested by the note in the data sheet 10.2.2.6 Auto reset on page 30(by the way, the schematic does not match what the words say and I did not follow what the schematic shows). But that doesn't seem to keep it from tripping.

Any suggestions or comments?

Thanks.

Richard Cummaro

Microchip Inc

(949) 280 5076

  • 0
    TI__Expert 4875 points

    Hi Richard,

    You could add a Schottky diode from DESAT to VCC2 to clamp the high level voltage during the transient in case it exceeds the VCC2 level. The Schottky is faster than the Zener. Additionally, you could see if increasing the blanking capacitor from DESAT to GND2 to generate a slower blanking time will prevent this short pulse from tripping the DESAT detection. Of course, the capacitor must be small enough to meet your total timing requirement for actual DESAT detection.

    What is the DESAT diode are you using?

    What is the series resistance and the blanking capacitance?   

    Regarding auto reset using the nRST pin, it is only relevant to reset a fault after it has already latched and after a short time interval. When a DESAT is detected the inputs are muted for 5 µs by internal circuitry. FLT can be reset, only after RDY goes back high after the mute time. This sequence is shown in Figure 46. nRST cannot be used to prevent a DESAT fault from triggering in the first place. The only way to deactivate DESAT is to short the pin GND2.

    Please let me know if you still experience issues after trying these modifications.

    Regards,

    Audrey 

  • 0 in reply to Audrey Dearien7
    Prodigy 40 points

    Thanks Audrey,

    The DSAT diode that I am using is: CD1408-FF11000.

    The  series resistor is a 1k as suggested by the data sheet.

    The blanking capacitor is 220pf and I also have a schottky diode (SS16) across the blanking cap as suggested by the data sheet.

    I will try your suggestion of the schottky diode to clamp the DSAT signal to the VCC2.

    I'll let you know how it works.

    Thanks,

    Richard

  • 0 in reply to Richard Cummaro
    Prodigy 40 points

    Sorry. Unfortunately this did not solve the problem. I would like to ask an additional question regarding the DSAT operation: If a DSAT is detected, is there a minimum time required before a shutdown is latched? Is it the 5us that was mentioned? If so, if there is a DSAT detected that lasts less than 5us(or some Tmin), will the chip shut down the output and then come back on? Thanks, Richard Cummaro

  • 0 in reply to Richard Cummaro
    TI__Expert 4875 points

    Hello Richard,

    Sorry to hear that did not work. I assume you were able to clamp the voltage at the DESAT pin to an allowable level, but it still exceeds the threshold voltage for some time? Does the nFLT pin still go low? Do you have some measurement you could share that shows the waveform at the DESAT pin?

    There is a glitch filter at the DESAT pin, typically a 330ns delay. So the DESAT voltage must exceed the threshold voltage for longer than tDS(GF), 330ns, in order to latch and initiate soft turn off. The soft turn off time depends on your load capacitance. In our datasheet, we specify a 2us turn off time from when VOUT drops to 10% with a 10nF load. At the same time, the driver cannot be reset until after tMUTE, about 5us, which begins after DESAT is latched. After tMUTE, the driver can now be reset using the nRST/EN pin.

    Regards,

    Audrey