BQ76200: on/off time of CFET and DFET

Hi Jamie,

You may be aware of the application note https://www.ti.com/lit/pdf/slua794 which describes component selection considerations with the part.  It is good to have a resistance in the DSG path to avoid transients into the part, but even when this is small the DSG pin/driver has an internal resistance which will limit the speed of the FET turn off.   

There are several times in turn off.

The propogation delay of the driver is short, shown in the BQ76200 data sheet figure 14. 

The transition time from the nominal DSG voltage to the point near Vgsth where the current starts to drop is exponential decay of the R-C, again part of the R is internal to the BQ76200, C is the FET gate capacitance.

The turn off of the FET where the current drops, (or the current trace rises in figure 16 of slua794).

The discharge of the PACK+ output pin where you want the FET to stay off, figure 16 of slua794 or figure 17 if the circuit does not allow the FET to stay off.

There are several ways to potentially speed up turn off:

1. Use an appropriately small resistance for RDSG
2. Add a transistor to clamp gate to source of the discharge FET either directly or with a small resistor.  A PNP has a lower Vbe than most MOSFET Vgsth, but requires current, so its turn off effect will be less than a MOSFET.  The P-channel MOSFET approach is voltage controlled but needs a Vgsth lower than the power FET and you would like its Vgs to withstand normal DSG voltage and some transients.  With either of these when the clamp transistor is off the DSG will not be driven so the Rgs resistor will complete gate discharge.  See Q5 in figure 3 of https://www.ti.com/lit/pdf/slua795 for an example of a P-ch FET to clamp off the gate.  In a DSG applicaton you would not have the blocking diode D4.
3. Clamp the discharge FET gate to PACK-.  This would require a timed control to enable the clamp after DSG_EN was low and to disable the clamp before DSG_EN went high. This could pull the gate of the power FET below the source, so a zener across the FET may be needed.  I don't know of an example circuit for this.

Keep in mind that when current is interrupted you will have an inductive response from the system.  V = LxdI/dt.  "I" is usually highese during short circuit and will depend on the cell capability. "L" is from the system construction and cells, "dt" is the switching speed and may be the easiest to control.  If needed you can clamp the voltage spike with various transient suppression circuits.