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LP87524B-Q1: Do the PMIC recovery automatic after drop to overvoltage status?

Part Number: LP87524B-Q1

Hello team,

Customer is asking if the LP87524B recovery automatic after dropping to overvoltage status? When the voltage goes high, the 87524 jump to over voltage protect status. then what happen if the voltage return back to normal? Will the 87524 return to normal working mode?

Thanks,

Wesley

  • Hi,

    Host processor has to clear the over voltage flag before regulators can be enabled again. If device is configured for enable pin control and enable pin is already high,I would expect that regulator gets enabled as soon as over voltage flag is cleared and input voltage is below OV limit. If regulator is set to be enabled through I2C, host processor has to enable it again.

    I will still check this with expert and get back to you if above my understanding is not correct.

    Regards,

    Murthy

  • Hello,

    I can confirm this is correct for the VANA overvoltage protection.

    Thanks.

    Regards,

    Tomi

  • Hello Tomi, Murthy,

    Thanks for your reply. 

    Is the overvoltage flag must be clean by host processor trough IIC? Or the PMIC will clear it automatic when the voltage goes lower than OV limit?

    Hence the processor is powered by PMIC 87524, during the owervoltage protection, due to the power is loss, the processor will be power off. How can the processor using IIC to clear this flag?

    Regards,

    Wesley 

  • Hi Wesley,

    Host must clear the OVP flag through I2C. Other way is going through reset cycle by setting NRST low for a moment, or by power cycling (setting VANA voltage below UVLO level will reset the logic). 

    Thanks.

    Regards,

    Tomi

  • OK. Thanks Tomi,

    Do you have any suggested workaround if using LP87524 to power up the processor. and the whole system has only one processor. How can this processor reset the PMIC while the over voltage protect happen?

    Thanks.

  • Hi Wesley,

    It might need some voltage monitor for the input to control the NRST, or logic circuitry to the NINT pin to allow reset. For example when interrupt happens the NINT pin is pulled low and this would cause the NRST to go low as well. But also thermal warning, and missing sync clock can cause interrupt, so that has to be taken into account. 

    Anyway the VANA OVP triggers above the normal operating range, so the input voltage should stay below the threshold. Is it possible to have some voltage limiting on the input of the LP8770 to avoid OVP triggering?

    Thanks.

    Regards,

    Tomi