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# TPS7A49: TPS7A4901 damaged when Cout shorted to GND

Part Number: TPS7A49

Hi there,

we use TPS7A4901: Vin=14.4V~19V, Vout=12V, Iout<100mA.  Css=CFF=10nF. SCH as below. Now we are at pre-production phase, there are 3 pcs damaged boards among 50 pcs during normal working.

All 3 pcs are Cout capacitor C10 or C11 shooted through (two ternimals shorted), which means TPS7A4901 output pin were short  to GND, and 2 pcs of TPS7A4901 is damaged., 1 pcs TPS7A4901 remains good because we found it was in over temp situation with IR camera and shut down the whole power in time.

The suspect should be Cout design. and I read the  page 17 of datasheet again but I have some confusion here ,hope some TI expert could help analysis.

On page 17 of datasheet, it says Cout has to be larger than 2.2uF for stability, and Cout(max) should also be limited by equation(7) and (8). However, Why tss(CL) is 140us (1/100 of 14ms ) and why Vout =2V in equation(8)?  I thought Vout should be 1.2V as page 16 wrote.

For equation 8. , in order to limit current not reach 500mA max during the whole soft-start process time (14ms), the Cout shoud be less than 14ms *500mA / 1.2V .

For our applicaiton, Cout-max = 0.5A*14ms/12V = 583uF. Seems our design is ok with this limitation. Seems our design is ok

Any suggestion is appreciated! Thanks! @

• Hi Yi,

On page 17 of datasheet, it says Cout has to be larger than 2.2uF for stability, and Cout(max) should also be limited by equation(7) and (8). However, Why tss(CL) is 140us (1/100 of 14ms ) and why Vout =2V in equation(8)?  I thought Vout should be 1.2V as page 16 wrote.

--You are right, given the conditions for this example, Vout used in equation 2 should be 1.2V.

For equation 8. , in order to limit current not reach 500mA max during the whole soft-start process time (14ms), the Cout shoud be less than 14ms *500mA / 1.2V .

-- The datasheet explains the reason for 140us as the followings:

For the soft-start to dominate the start-up conditions, place the start-up time as a result of the current limit at two decades below the soft-start time (at 140 µs)

This is to ensure during the startup, the device will not running into the current limit and allows enough margin over temperature and other variations.

I can see your design has a combined >66uF, and it may be okay but it's much higher than the datasheet example, the output capacitance max should be calculated as Cmax = 140u x 0.5A / 12V = 5.83uF; with 66uF, I would recommend taking the load current waveforms to see how it looks during the startup.

For the damage on the output capacitors, I see you have 25V rated capacitors, to damage the caps, you may have a high AC spike >25V in the application. Is it possible for you to provide waveforms that show Vin, EN, Vout, Iload for me to review?

Regards,
Jason Song

• In reply to Jason Song:

Hi Jason, thanks for patient reply. I did noticed these words and this 1/100 is exactly what confuse me.

Quote: "For the soft-start to dominate the start-up conditions, place the start-up time as a result of the current limit at two decades below the soft-start time (at 140 µs) This is to ensure during the startup, the device will not running into the current limit and allows enough margin over temperature and other variations. "

I think the soft-start cap is charged by internal current source linearly, to control Vout ramping rate, so as to control the Inrush current during start-up ramping. For a given Css, the correct ramping time is determined by tss = Css*1.4 =14ms; and for given Cout, the I_inrush = Cout*Vout / tss. The goal is to ensure I_inrush < 500mA in the whole ramping process, so Cout should be limited by Cout(max) < 500mA*12V/14ms = 583uF

From another point of view, if we use tss(CL) (which is 1/100*tss) as in eq.(7-8) , this indicate that Vout will ramp to 12V in 140us. this is not going to happen (and not allowed) as we already designed soft-start function with Css=10nF which will be linearly charged to VREF durign start-up and correspondingly the Vout will ramp to 12V within designed tss. So I think the assumption "the short start-up time caused by the current limit at two decades below the soft-start time" seems to be  ungrounded.

I also searched TI application notes like slva670a , it mainly talks about I_inrush = Cout*Vout / T < I_limit, where T should be designed / controlled in oder to be slow (soft) to ensure adequate inrush current.

Here is ramping waveform of 12Vout days ago with no-load. I thinks it's ok, you can see tss=~40ms, including the Cff influence on actual tss time and consistent with TI doc SBVA042.

Some other thoughts:

1. This 4901 damage problem is occasionally events, like I said , about 3/50 probability. So I am bothered by not able to capture the scene because it is not always happening. But this could be caused by incorrect design, or maybe the 22uF/25V cap have some quality issue, both are risk before we move on to  massive production phase.

2. I checked again, 12V's total Cout value with all downstream circuits should be about 106uF. Today I doubted the inductor L1 and L7 ( pic below,  U11 is disabled with its pin4=low) may occasionally generate induced voltage by inrushing current during start-up.

3. PSRR is important for us, if you limit Cmax = 140u x 0.5A / 12V = 5.83uF, this would conflict with datasheet recommendation the Cout > 10uF for better AC performace and better PSRR.

I will try to do some more tests and post waveform as you mentioned in the next few days. Thanks again.

• In reply to Jason Song:

I rethinked, the sentence "For the soft-start to dominate the start-up conditions, place the start-up time as a result of the current limit at two decades below the soft-start time (at 140 µs)" may mean this:

IF the device expirenced over current limit during start-up, the max current will remain 500mA ( device feature), we wish to limit the time of current limiting to be as short as possible, the short tss(CL) is , the less overheat the device will suffer , and tss(CL) is aimed to be 1/100 of tss:

tss(CL) = Cout*dv/di < (tss/100),

in this equation, di=i_limit=500mA during current limiting,

However,  under this circumstance,  I think dv may not necessarily be Vout. Because,  if dv=Vout, this equation would indicate that it only takes tss/100 for Vout to rise from 0 to 12V, and this means Css is not working at all.

• In reply to Jason Song:

Hi Jason, we clamp a current probe on R8 position. pls see I_R8 waveform as below CH4.  and CH1=enable, CH2 = L1 left pin, CH3 = L1 right pin (TP3).

We enable 12V only, and output voltage 12V and its ramping process seems to be ok. but there are something strange here.

1. abnormal current spike (>1A) occurs at 15ms after EN signal. I think this is a possible reason that 4901 was damaged. but not sure how it comes from.

then we removed L1, LM2733 , and L7, and D7,  but nothing changed.

2. after soft-start , the average DC current is about 200mA, which means TPS7A4901 is under larger current stress, which is very surprising.

we use VCC12V to powering

(1) 3 pcs UCC38C43D: disabled by pulled comp pins low. which means it power consumption is quite small, about 0.1mA per chip.

(2) 7 amplifier OPA197, most of them are used as voltage follower, and the power consumption should be small ,too.

(3) 1 LM2733.  we tried removed LM2733 , and L7, and D7, the CH4 current waveform is the same.

(4) 1 LM339A, its output pin is pulled up by 3.3V.  12V power consumption should be small ,too.

self note:

the current spike 15ms after enable signal seems happned just  at when VCC12V rises to 8~9V. this is happned to be UCC38C43's VDD pin start threshhold voltage(7·9V,typ.8.4v).

Hi Yi,

Thanks for sharing such details. I agree with you when the startup time is set for 14ms and using a 1/00 of 14ms which is 140us for the maximum capacitance calculation to make sure the part is not running into the current limit is very conservative. This is the reason for me to ask to take the waveform that shows the output current to see if the soft-start has been affected. Based on the waveform, during the startup, the in-rush is not affecting the soft-start output ramping, so the LDO should have no issue driving the capacitance in the system.

When the TPS7A49's output current is settled at somewhere near 220mA, this indicates the LDO could already be in the current limit. Since you mentioned the application only requires <100mA of load current from the LDO, what is actually taking the extra current that keeps the LDO in the current limit? Are all 50 pcs shows such a high current output? Continuously running the LDO at higher than the rated current could significantly affect the reliability of the device and it may result in a shorter lifespan.

For the current spike observed in your test, it can also be understood as the load current is shooting up higher and the internal LDO's current limit loop starts kicking in to clamp the output current at LDO's current limit. From the plot, the spike happened when the output of the LDO reached about 10V, in the system, do you have anything that will be turned on at around 10V? Your self note explains that at least that's where the UCC38C43 turns on and this could explain the spike and the current is then being clamped by the LDO's current limit loop.

Regards,
Jason Song

• In reply to Jason Song:

I removed all UCC38C43D on board, and the current spike disappears, which proved my "self-note" is correct, the current spike occurs right at the time when 38C43 VDD rise above 8.4V. But how to solve this problem seems hard, there seems nothing much we can do with 38C43. I would post a new thread on power section of this forum to consult expert on 38C43.

And as you mentioned "When the TPS7A49's output current is settled at somewhere near 220mA, this indicates the LDO could already be in the current limit. ". I agree with this, so I will need to find out how these current composed of.

I think one possible solution is to relpace 4901 with another device with more current capabilitiy, do you have any recommendation? better with pin-to-pin footprint compatible. Thanks!

• In reply to Jason Song:

hi Jason, the detailed waveforms are on this post. for your reference.