Dear Support,
Our datasheet mention that we can use the inner layers to create a high frequency bypass capacitor between GNDP and GNDS. In the case of we get a large GND separation, as for the external layers, can we add a physical capacitor? would you have any recommendation on this capacitor? Are there any EMC/EMI or other parameters which could be affected?
A second point about the layout is: what are the consequences of getting signal traces on the bottom layer of the PCB, in the same area of our UCC (placed on the top)?
I'll be able to send you more details in private, if needed.
Regards,