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UCC12050: Layout and bypass capacitor

Expert 3795 points
Part Number: UCC12050

Dear Support,

Our datasheet mention that we can use the inner layers to create a high frequency bypass capacitor between GNDP and GNDS. In the case of we get a large GND separation, as for the external layers, can we add a physical capacitor? would you have any recommendation on this capacitor? Are there any EMC/EMI or other parameters which could be affected?

A second point about the layout is: what are the consequences of getting signal traces on the bottom layer of the PCB, in the same area of our UCC (placed on the top)?

I'll be able to send you more details in private, if needed.

Regards,

  • Hello,

    1. You may use a 100nF to 500nF or something for high-frequency filtering on the external layers if the spacing between them is large. It is important for this y-capacitor to be a film cap to meet the isolation standard and breakdown ratings. It would have implications on the EMI testings because now instead of the whole plane to conduct noise the signals will be forced on a y-cap connection point. It is highly recommended to stick with spacing in the stitching layer as described in the datasheet for the most efficient EMI results.

    2. There are two major issues with having signal traces at the bottom layer of the controller: Firstly, the isolation barrier. Secondly, running the traces from underneath the controller always puts the internal signals at a risk of noise injection from the external trace. I would strongly suggest not doing so.

    Regards,

    Sonal

  • Thanks Sonal.

    I'm switching in private message, to share you more details.

    Regards,