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UCC21710-Q1: transistor connection

Daria Kiseleva
Intellectual 1440 points
Part Number: UCC21710-Q1
Other Parts Discussed in Thread: UCC21710, , UCC21732-Q1

Good day,

I couldn't find any information on how to connect several transistors to gate driver (clmpi pin) for UCC21710. Could you help me with this?

Thank you,

Daria

  • 0
    TI__Genius 10652 points

    Daria,

    Sorry, I dont understand exactly what you mean by

    Daria Kiseleva said:
    connect several transistors to gate driver (clmpi pin)

    Are you referring to how to use connect when using external buffer (via BJT) to increase drive strength?

    Best

    Dimitri

  • 0 in reply to dimitri james
    TI__Intellectual 1440 points

    Hi Dimitri,

    One of my customers plans to use UCC21710-Q1, they connected 2 SiC Mosfets as on schematics below. The question is if the connection of clmpi(7) is correct in this case. Thank you.

  • 0 in reply to Daria Kiseleva
    TI__Genius 10652 points

    Daria,

    Thanks for providing the schematic!
    We don't recommended to have anything in series to the CLMPI pin, I noticed that schematic have diodes VD3-VD6 on there. This, at very least, would cause Miller clamp to turn on earlier each cycle due to VF of diode, and potentially other problems as well.

    I would recommend to remove the Diodes, and directly connect both gates to CLMPI. With this configuration, extra attention should ensure that both drivers have virtually equal-length/symmetrical layout of turn-on, turn-off, and clamp paths from the gate

    Parasitic inductance has potential to cause paralleled SiC fet gates to begin to mutually oscillate with a >1 gain which can damage the gates. So, reducing the inductance as much as possible is a top priority via layout when driving parallel . Suggest placing gate resistor as close as possible to the gates also. And reducing CLMPI trace length as much as possible, and making sure this is also symmetrical for both FETs.

    Another option is to take a use UCC21732-Q1, which has external miller clamp. Two different external FETS for each gate could be used which might be a better approach. The only difference is the clamping voltage is measured at the output pin of the gate driver rather than directly at the gate. Splitting the clamp FETs would ensure that those gates remain separated as much as possible,  which isn't able to be done with UCC21710-Q1 when using the

    There are other ways to prevent issues with parallel FET driving: 1) a resistor placed between drain and gate 2) a cap placed between drain and gate, but they cause loss of efficiency and limit switching frequency. As a "last resort", only if the oscillation becomes problem, ferrite bead could be placed at each gate.

    I hope this helps, let me know if you have any followup or other questions on this!

    Best

    Dimitri