HI Team,
What's the delay time for CL pin to react and limit the current in an over current event? is there any spec relate to this in the datasheet?
Customer test it and found it's around 2.66ms, could you please help to confirm?
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HI Team,
What's the delay time for CL pin to react and limit the current in an over current event? is there any spec relate to this in the datasheet?
Customer test it and found it's around 2.66ms, could you please help to confirm?
HI Antony,
In datasheet we also have a deglitch time when current limit occurs, what's this spec for?
Customer is asking if it'll trigger a OCP event when first power up, and there is capacitance on the load. If the large short period inrush current might trigger an OCP event, and is there any detailed time spec for this?
Thanks
Hi Ted,
The deglitch time when current limit occurs tCL(deg) is the time difference between the current limit occurring and the current limit being reported on the status pins such as /Fault, /STX, and CS pins.
Yes, the current limit can be triggered by the inrush current. The time it takes will depend on the size of the capacitor.
You can find more information in the following app note on Driving Resistive, Inductive, Capacitive, and Lighting Loads with Smart High Side Switches. Let me know if there are further questions.
HI Anthony,
So for deglitch time, if the current goes up and triggers the CL limit, and goes down below the limit within the tcl(deg), will the fault reported out on the FAULT pin etc.?
And in this case, will the current being limit by the HSS if it only happen within the tcl(deg)? Will the HSS start to clamp the current after the tcl(deg) timer or it start to clamp immediately once the CL limit is reached?
Thanks
Hi Ted,
Communication for this thread will continue over email. I will update this thread if a conclusion is reached in email.