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BQ40Z60: Discharging related issues

Part Number: BQ40Z60

I'm currently using the TI BQ40Z60 board.

While performing the discharging process it is observed that the cell 1 and cell 4 are stressed more and are showing a comparatively lesser voltage as compared

to cell-2 and cell-3. The gg.csv as well as the snapshots of the FET are shown along with the cell-1 ...cell-7356.Learncycle_BQ40Z60_4S1P_3200mAh_registers.gg.csvdischarge based FET's set.csv4 voltages

  • Hello Mihir,

    There was a problem with your discharge CSV file, it was blank when I opened it.

    Sincerely,

    Wyatt Keller

  • discharge based FET's set.xlsxHello Wyatt,

    Actually the csv file just had the image of the bq studio dashboard while performing the discharge cycle. 

    Check out this xlsx file for the same 

    The dashboard showed cell 1 and cell 4 having lower voltages while cell 2 and cell 3 were having comparatively higher voltages.

    The reverse results are obtained when I use the same EVM for charging purpose.

    Regards 

    Mihir

  • Hello Mihir,

    Could you provide the schematic of system and also the board layout? Can you check to see if the cell voltages remain that separated when the batteries are relaxed? A log file of a battery cycle with a discharge of 30 minutes and relax of 2 hours would let us see this as well.

    Sincerely,

    Wyatt Keller

  • Hello Wyatt,

    Please find the attached log file for the variation in cell while the cells are getting discharged as well as when they are getting charged.

    0336.Main_Discharge_09_06_2020_3200mAh.log4452.Learncycle_BQ40Z60_4S1P_3200mAh_registers.gg.csv

  • Hello Mihir,

    We have looked through your log file and .gg.csv file and have a few theories for the issues:

    Interconnect resistance

    • Please provide block diagram of how you hooked up the cells.
    • Measure the interconnect resistance between VC2 to VC3 connect points.
    • Measure the interconnect resistance between VC3 to VC4.

    Cell to cell variation

    • Take apart the individual cells, charge each to full, log with same discharge current, temperature and to terminate voltage and determine if there are discrepancies in Qpass. This will tell us if the resistances vary inside the cells are causing the inconsistent cell voltages.

    Enabling balancing

    • It could be the cells are inherently out of balance. The gg.csv file attached shows an update status of 0x04. This means no field Qmax and no learning cycle has been completed. Balancing won’t be enabled.
    • Go ahead and complete a learning cycle after the first two theories have been ruled out.
    • Once learning is complete, enable balancing to see if the voltage variations are reduced.

    One of these is most likely the issue, see if these help debug your system.

    Sincerely,

    Wyatt Keller

  • Hello Waytt,

    • With regards to the interconnect resistance, I dont suppose there is a provision provided in BQ40Z60 to have any sort of interconnect resistance. 
    • I went through the post https://e2e.ti.com/support/power-management/f/196/t/643261 and even tried to understand what actually is interconnect resistance. 

    • Currently our cell connection layout looks a bit like as shown in figure above, currently we don't have any interconnected resistance in our BQ-board.

    On your suggestion to charge the cells completely individually and perform the discharging cycle I've already mentioned to you that that has been performed from my end in the post https://e2e.ti.com/support/power-management/f/196/t/911464

    The flags as and how those need to get set are happening, how ever after the discharge cycle and 5 hour long rest when the cells are again charging the cell voltage is restricted to just below 4100 mV, what do you think in the reason for the same. Please go through the gg.csv and log file as well as the matlab based circuit diagram for further analysis provided in the post https://e2e.ti.com/support/power-management/f/196/t/911464 for reference. I suppose some of the setting issue is happening that might be causing all this sort of trouble  

  • Hello Mihir,

    The interconnect resistance would be a part of your board's layout, not from the schematic. The traces/wires must be large enough not to cause much IR drop across them, otherwise it can lead to similar graphs as this.

    There was no mention of doing a Qmax test on the cells in the previous thread, are you certain they are all of equal capabilities?

    Make sure there is minimal noise on the HSRN and HSRP pins as well, you mentioned in the other thread you can reach your desired charge current by changing the threshold, can you try doing this and completing a learning cycle to see how the gauge is operating?

    Sincerely,

    Wyatt Keller

  • Hello Waytt.

    In your previous posts you mentioned related to interconnect resistance and cell to cell variation.

    I went through the capacity data as you mentioned and obtained that there is a variation of 100mAh between the cell 3 and cell 4 

    because of which we might be observing the voltage variation. Similarly, there is also some interconnect resistance we are having nickel 

    plated copper busbars for cell connection and I tried using multimeter to obtain the resistance and got the values pretty high

    I've asked for the datasheet to the vendor from whome I've obtained the busbars. Meanwhile a new 4S cells with 2650 mAh discharge capacity each 

    have been selected again and are going through charge cycle.

    I will perform the learning cycle again and keep you posted on the same. 

    Thanks 

    Regards

    Mihir

  • Hello Mihir,

    I hope once you get the learning cycle completed and new bus bars your system will work well.

    Let us know if you have any more questions!

    Sincerely,

    Wyatt Keller

  • Hello Wyatt,

    In order to remove all the wiring issues we tried doing spot weld in order to have the least resistance while doing the 4S1P connections. 

    I'm currently working on a newly bought BQ40Z60-EVM, I thought my older one might had an issue.

    Currently even when all the cells are at same voltage level when they are 100% charged using a neware recycler, even now when I perform 

    the discharging / charging process for my learning cycle there is a gradient in a voltage as I mentioned earlier, i.e. the cell 1 and 4 had a lower voltage 

    while dicharging in comparison to cell 2 and 3 voltage and the completely reverse phenomenon is observed during the charging process. The cell now that I'm using are having the same  discharge capacity as I observed the cycling data of the cells also cells are newly bought cells

    Please respond the current issue.

    Thanks 

    Mihir

  • Hello Mihir,

    Can you post the new logs and .gg file before and after the cycles? Is the voltage separation exactly the same or less? If it has diminished I would try to get the learning cycle completed and enable the cell balance.

    Sincerely,

    Wyatt Keller

  • Hello Waytt, 

    If I try to resolve one problem in this BMS the other one pops out of no where.

    Consider the following gg.csv file and .log file during the discharging cycle. 

    It now so happens that the charging cycle is not happening neither any flags that show what is the issue related to the same

    The charger is connected as can be seen from CHGR flag but still the charging is not happening 

    Discharge_test_26_06_2020.log4S1P_BQ40Z60_2650mAh_register_config.gg.csv

  • Hello Mihir,

    Could you upload the individual cell tests you performed? Could you also try performing the tests with the cells in parallel?

    It seems your cells are not fully charged to the same design capacity from the tests as the voltage spread is very large.

    Sincerely,

    Wyatt Keller

  • Hello Wyatt,

    What do you mean by the voltage spread is very large...are you taking about the working range of the cell

    Thanks 

    Mihir

  • Hello Mihir,

    The spread between the cells, when one cell hits the termination voltage other cells are over 500mV higher than that. Somehow there is still interconnect resistance or the cells don't have the same capacity when charged to full it seems.

    Sincerely,

    Wyatt Keller

  • Hello Waytt,

    Sorry, I thought by doing spot welding the interconnected resistance might have reduced and

    actually that was not the case. The voltage drop between battery positive and the VC5 pin was 

    50mV while the voltage drop between the battery negative and VC1 was 90 mV(approx) this used 

    to cause the error during the charging as well as during the discharging cycles. 

    So yes the interconnect resistance is the cause for the fault that I was observing. Similarly the charging and discharging 

    learning cycles now are happening and I've observed Q update flag set to 06.

    Still there is one more issue which is pending is that of the charging current. The charging current that 

    I've set is 1300 mA in my application case and when I observe the charging current it is always approx

    300 mA lesser than the set current (at different voltage and temperature I've used 1300 mA during my normal 

    cycling while I've kept 650mA during precharge but what I've observed is the current is 1000 mA (approx) during 

    normal cycling and around 250 mA during precharge period 

    Thanks for having patience and responding every time Waytt

    Regards

    Mihir

  • Hello Mihir,

    I'm glad to hear the problem of the cell voltage separation is resolved.

    The bq40z60 doesn't have a way to calibrate the sense resistor for the charging current, I would recommend either adjusting the software or changing the sense resistor for it to match the charge current you set.

    Sincerely,

    Wyatt Keller