The output of the DCDC converter stopped and the UCD3138 reset during use in a EMC noisy environment. When I checked the register of SYSESR after reboot, it was 0x0000.
According to Technical Reference 11.20 System Fault Recovery Basics, "if a reset occurs and none of the bits are set, then the cause is the watchdog timer."
However, because the register Watchdog Control (WDCTRL) is set to Default *), reset by watch dog timer should not work.
1. Even if the register Watchdog Control (WDCTRL) is set to Default *), does Reset by the Watchdog timer occur?
2. If the register Watchdog Control (WDCTRL) is set to Default *), may there be a reset that causes SYSESR to be 0x0000?
3. If you have a concrete example, please advise.
4. If the register Watchdog Control (WDCTRL) is set to Default*) and the CPU freezes, can the peripheral, DPWM module continue operating?
*) CPU_RESET_EN: 0: Watchdog Reset does not reset CPU.