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TPS25940: Capacitor type Suggestion for dVdT pin

Part Number: TPS25940

Hi Team,

We are using TPS25940 eFuse as a Super Capacitor Charger in our design.

From the calculation it is coming around 100uF dVdT Cap value which needs to be connected for dVdT pin for 500mA output charging current.

Since it is larger value and also for reducing the cost, we are planning to go with Aluminium Electrolytic Capacitor type.

Please confirm Aluminium Electrolytic capacitor type suitable or not for this place.

Or do we need to go with Ceramic/Tantalum type?

Please suggest.

Thanks & Regards,

Muneeswaran R

  • Hi Muneeswaran,

    Instead of using the dvdt cap to limit the inrush current to 500mA, you can set the current limit itself to 500mA. This is because the maximum current you will ever allow through the efuse to charge the super cap is only 500 mA.

    In case you like to use the dvdt functionality with an electrolytic cap, it is better that you consider a electrolytic cap which has low ESR. 

  • Hi Praveen,

    Is this the correct solution for Charging Super Capacitor with current controlling by using I(LIM) pin setting?

    What is the advantage/disadvantage between these two? dv/dt control & I(LIM) control.

    Regards,

    Muneeswaran R

  • Hi Muneeswaran,

    By using dvdt control, you are indirectly limiting the current during startup. Generally, dvdt current is set to a value lower than current limit because most of the applications require higher load current in steady state operation. But in this case, charging the super cap itself is the main operation and I don't think you will require higher load current than 500 mA.

    Below are the advantages of using current limit rather than dvdt control for charging supercap,

    • You can get rid of the high dvdt capacitance. To disable dvdt, you can leave the dvdt pin floating. The device will automatically start in current limit
    • dvdt capacitor adds delay in startup. This is because the voltage on dvdt is reflected on Gate of the internal FET with some gain. The FET doesn't start conduction until its gate voltage goes above its thershold voltage Vt. This delay is not expected if you startup with current limit. For example, you can refer to Figure 11 of the app note http://www.ti.com.cn/cn/lit/an/slva920/slva920.pdf?ts=1591629931797&ref_url=https://www.google.com/

  • Hi Praveen,

    Thanks for making me understanding.

    Now we have decided to go with Current limit method.

    Thanks for your support. 

    Regards,

    Muneeswaran R