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UCC28780: How to shut down UCC28780

Tak
Intellectual 480 points
Part Number: UCC28780
Other Parts Discussed in Thread: UCC27712

I designed the circuit with the combination of UCC28780 and UCC27712D.
I would like to have a specification that shuts down the main power supply when an abnormality occurs on the secondary side. As a way of realizing it, first get the status from the photocoupler and use it together with a latch circuit (such as a one-shot multivibrator) to completely stop the operation of the UCC28780.

I am worried about the processing method after this.
I am wondering which pin should be used to shut down. The UCC27712 does not have an ENABLE pin, so it seems difficult to shut down.
So I'm thinking of using NTC (9pin).
I'm thinking of preparing a 10kΩ resistor in parallel with the NTC thermistor and forcibly setting it to 10kΩ or less in the event of an abnormality.

Is there a more practical way?
If I force the RUN pin LOW, it won't shut down, right?
If it can be realized with the RUN terminal, it may be better.

B.R. Tak

  • 0
    TI__Mastermind 26840 points

    Hello Tak,

    Thank you for your interest in the UCC28780 ACF controller.

    Section 7.4.10.3 of the UCC28780 datasheet (page 32) describes the behavior of the NTC pin OTP function.  It can be used as a shutdown pin as you suggest, but be aware that it is not an absolute shutdown.  As long as Vntc is less than 1V, the controller will cycle through VDD charge and discharge and will test the start-up conditions with 3 brief test pulses at the peaks of the VDD cycling.  There is almost zero transfer of power to the output during these test pulses, but the lower MOSFET does switch for the 3 tests.  Even though the MOSFET switches briefly, the output remains unpowered until the NTC pin is released.  The NTC input can be pulled to GND directly with the photo-coupler transistor, without series resistor, because the NTC current is limited to 105uA.     

    However, if your shutdown requirement is for no switching at all during the fault condition, then I suggest to pull the REF output down to GND with a transistor.  This method appears to violate the 5-mA Absolute Maximum rating of REF source current, however that is a continuous load limit. The REF circuit is internally current limited to about 15mA and when pulled below ~4.5V the controller will shut down.  The 15mA will rapidly discharge the VDD to the UVLO threshold where the REF is turned off.  Then the controller will attempt to restart by charging VDD up to 17.5V and turn on REF again.  Since REF is held low by the external transistor, it will pull VDD down to 10V without any switching.  This start-up attempt sequence will cycle indefinitely until REF is released.  The duty-cycle of the overload on REF will be small.  Since VDD stays above ~10V, the fault transistor can stay latched on until input power is removed and the latch loses power.   

    But be aware that VDD is charged by the bulk capacitor, so even after removing AC power, it will continue to cycle in restart attempts until the bulk cap is depleted. This can take a long time, depending on the size of the bulk cap.  Alternatively, latch bias-power may be derived directly from the AC line, but that circuit design may be cumbersome.

    Regards,
    Ulrich

  • 0 in reply to Ulrich Goerke
    Intellectual 480 points

    Dear Ulrich

    Thank you for your helpful advice.
    Your answers are always really great.

    My concern has been resolved.

    I use the REF terminal as you suggested.
    Also, thank you for telling me the detailed internal circuit specifications.
    (Constant current circuit etc.)

    B.R.Tak