For the evaluation board, is there benefit of each capacitor being individually grounded by vias to the inner layer ground plane as opposed to the vias attaching to a top layer ground geometry, first, then down to the ground layer? (Referring to document SLVUBG0–July 2018, Figure 2 top layer). Vout is flooded on the top layer whereas the capacitors' ground pins are "islands".
Our 4-L PWB layout currently has vias to geometries as shown below and I'm wondering whether or not to modify the grounding...?
Thanks,
Fred