UCC24612: SR(Synchronous Rectifier) FET curcuit

Hello Dae Hyun ,

Thank you for your interest in the UCC24612 SR controller.

In my opinion, I think your SR design should work in general but I have some concerns:

1. MOSFETs in parallel should have a resistor on each gate to dampen any possible ringing between FETs due to wire bond and pcb inductances and gate capacitances.
   I suggest to use 10-ohm in series with each gate. You can connect the 10kR pull-down at the input junction where the 3 gate resistors tie together.

2. The “Kelvin” connections to the sources of each FET for VS sensing is a good idea.
   I recommend that you do the same for the drains of each FET for VD sensing.

3. The MOSFETs you chose are very low resistance parts, with high gate capacitance.
   Three of these in parallel are less than 1mR, with huge capacitance. I am concerned about over-design. You gave no load information, but design guidance in the UCC24612 datasheet (section 8.2.2.1, page 24) suggests choosing Rds(on) > 50mV / (0.5*I_sec_peak).
   Using lower Rds(on) than this costs more but does not improve efficiency much and requires more power to drive the gates.

4. Each FET gate charge is 41nC. 3 in parallel is 123nC at 100kHz = 12.3mA average bias current, plus ~1mA for the SR controller.
   The controller VCDS(+) voltage is not shown, but if 10V, then 10V x 13.3mA = 133mW mostly dissipated in the controller. If switching frequency and/or bias voltage is higher, then scale the loss accordingly. Check the junction temperature rise for this power level, based on the SOT-23-5 thermal characteristics.

5. Unless your I_sec_peak is really high to require three 1-mR FETs in parallel, consider using smaller FETs (higher Rd(on)) and/or fewer in parallel to do the job.

6. I suggest to also consider using the UCC24624 dual SR controller, which is specifically optimized for this kind of LLC topology. It also has a 35mV regulation level instead of 50mV. See Section 9.2.2.1 (page 22) on Rds(on) selection guidance.

   Regards,

   Ulrich

Hi Dae Hyun,

In your schematic diagram, you have 3 MOSFETs in parallel for reach leg of the LLC output.
These FETs are listed as CSD18450Q5B which show total gate charge = 41nC at Vgs = 10V.  3FETs in parallel will use 3 x 41nC = 123nC.

In my reply point #4, I chose 100kHz for LLC switching frequency to simplify the calculations, because actual fSW was not available at the time.
Each SR controller must transfer 123nC every switching cycle to the FET gates, so 123nC x 100kHz = 12.3mA.

In your reply, you indicate that fSW = 150kHz.  In reality, the UCC24612 clamps VG to 9.5V, so Vgs is not 10V.
The CSD18450Q5B datasheet, Figure 4 shows Qg at 9.5V = 40nC, so actual gate-charge current per SR controller = 3 x 40nC x 150kHz = 18mA.

18mA x VCDS(+) = power dissipation in each SR controller.
If VCDS(+) = 12V, then you may consider to add a resistor between VCDS(+) and the VDD pin of each SR controller to drop 1~2V, and reduce dissipation in the controllers. 1V/18mA = 56ohm, 2-V drop = 112ohm.  This can reduce loss in the IC by 36mW, and puts it into the resistor.  Higher resistor value will reduce IC loss more, but will also reduce Vgs to the SR Fets.  So you can try increasing resistance until overall efficiency drops, then choose the optimal value.

Regards,
Ulrich