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LM5021: LM5021

Part Number: LM5021

I plan to use two LM5021 with synchronize function as the interleaving mode.

There is no timing chart between sync puls and PWM in the datasheet.

And 100pF capacitor must be used when sync pulse add through to the RTpin. 

It's difficult to make a 15nS to 150nS sync pulse because time constant of 100pF and RT value

is much larger.

I would like to know the timing chart and can I use the smaller capacitor less than 100pF to add

the sync pulse.

Best regards.

TAKASHI 

  • Hello Taka555,

    Thank you for your interest in the LM5021 PWM controller.

    I'm sorry that there is no timing chart available for this part.  However, I believe that the datasheet recommendation of 100pF is intended to cover a wide range of RT values, including those with low resistance for very high frequencies. 

    If your application uses a relatively high resistance for RT (low frequency) then I believe that the sync cap (Csync) can be lower than 100pF.
    The main design target is to ensure that the sync pulse peak on RT is >3.8V for a duration > 15ns.  Choose a Csync that can meet these requirements.

    Regards,
    Ulrich

     

  • Ulrich Goerke said:

    Hello Taka555,

    Thank you for your interest in the LM5021 PWM controller.

    I'm sorry that there is no timing chart available for this part.  However, I believe that the datasheet recommendation of 100pF is intended to cover a wide range of RT values, including those with low resistance for very high frequencies. 

    If your application uses a relatively high resistance for RT (low frequency) then I believe that the sync cap (Csync) can be lower than 100pF.
    The main design target is to ensure that the sync pulse peak on RT is >3.8V for a duration > 15ns.  Choose a Csync that can meet these requirements.

    Regards,
    Ulrich

     

    Hello Ulrich.

    Thank you for your advice.

    I try to check the timing by testing LM5021.

    Regards,

    TAKASHI