• State
  • Locked Locked
  • Replies 7 replies
  • Subscribers 63 subscribers
  • Views 144 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

LM3481: UVLO formula to back calculation shutdown voltage

LM3481: Variation of Vuvlo & Iuvlo parameters w.r.t temperature

Chaitanya Koppaka
Prodigy 80 points
Part Number: LM3481

Hi TI,

I'm designing the UVLO circuit using LM3481 for my application.

To verify the worst case limits of enable & shut down of my converter, I would like to know how Vuvlo & Iuvlo parameters vary w.r.t temperature. 

From data sheet I read that Iuvlo will vary from 3uA to 6uA over -40C < Tj < 125C. But at what temperatures do the minimum and maximum will happen?

Similarly for Vuvlo, at what temperature the UVLO comparator threshold maximum and minimum will happen?

Any relevant graphs of these parameters' variation w.r.t temperature are very much appreciated.

Thanks

Chaitanya K

  • 0
    TI__Expert 7450 points

    Hi Chaitanya,

    Thanks for your interest in LM3481.

    I will check with our designers and get back to you.

    Thanks,

    Yinsong

  • 0 in reply to Yinsong Cai1
    TI__Expert 7450 points

    Hi Chaitanya,

    This data is not available. Furthermore, the UVLO threshold is based on the bandgap voltage which is supposed to be flat over temp so we cannot give trend as far as high UVLO at high or low temp.

    A trimmed bandgap is ideally flat over temp but from part to part it can be slightly positive TC or slightly negative TC so again, we can not give a definitive trend.

    Thanks,

    Yinsong

  • 0 in reply to Yinsong Cai1
    Prodigy 80 points

    Hello Yinsong,

    Thank you very much for your reply!!

    This piece of information is crucial for me to do worst case analysis. So, I request you to provide a "ppm" number (an approximate value, out of your experience, can't be a documented one) of which the UVLO maximum & minimum can happen as I can't take a blind guess for my calculations.

    Are Iuvlo, Vuvlo dependant or independant? In other words, Iuvlo_max & Vuvlo_max occur at same time?

    Thanks,

    Chaitanya K

  • 0 in reply to Chaitanya Koppaka
    TI__Expert 7450 points

    Hi Chaitanya,

    Sure. Let me see what I can get from our designers.

    Thanks,

    Yinsong

  • 0 in reply to Yinsong Cai1
    TI__Expert 7450 points

    Hi Chaitanya,

    Here is what I got.

    • The UVLO voltage is directly based on the reference voltage and is flat over temperature. 
    • The current value will depend more on the resistor value which is not corelated to the Vref tempco. In other words there is no correlation between the UVLO voltage and current but both should be ideally flat over temp.

    Thanks,

    Yinsong

  • 0 in reply to Yinsong Cai1
    Prodigy 80 points

    Hi Yinsong,

    Thanks again for your efforts in bringing this information to me.

    Just to confirm my understanding of your second statement, are you referring "the resistor value" to the R8 resistor in potential divider (see image attached).

    What is the equation that governs the Iuvlo current?

    Thanks

    Chaitanya K

  • 0 in reply to Chaitanya Koppaka
    TI__Expert 7450 points

    Hi Chaitanya,

    The resistor is inside the chip that relates to the current. We may not be able to go into too much details about the design inside the chip.

    But the conclusion holds that there is no correlation between the UVLO voltage and current but both should be ideally flat over temp.

    Please let me know if you have any questions.

    Thanks,

    Yinsong