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TPS63020: Cascaded regulators misbehaving

Part Number: TPS63020

Hi TI support

Strange behaviour hoping to get some support with. We've cascaded two TPS63020 to avoid single fault condition with a shorted input regulator. VSwitched input is 3.8V and VSYS output of stage 1 regulator is 2.77V. This is fed directly into a second regulator which is supposed to have a 2.8V output. 

When in this configuration, the Vsys = 2.77V as expected, however 2V8 is significantly under voltage (approx 2.4V). 

If we bypass the first regulator and apply 2.7V to VSys through a regulated power supply, the secondary regulator behaves appropriately and 2V8 = 2.8V.

So, in short, individually they are fine, cascaded they seem to misbehave - we've worked up multiple boards with this same issue and hoping to get some clarity on what we're doing wrong?!

Screenshots of the corresponding schematic - apologies for the scale & symbol difference, they're on different sheets in our design.

  • Just noticed my schematic did not attach to the last message. Retrying:

  • Hi General:

    May I know what's the load condition during your test? And may you share the waveform of VSYS, V2V8, and the layout with us,

    Additionally, I'm wonder the purpose that you cascaded two device to avoid the short risk. Why not use a efuse if necessary?   (Just curious...)

  • Hi Minqiu - thanks for your quick reply

    1stly, load condition is light in the testing. Maximum 300mA draw to a microcontroller. 

    Can quickly share the layout as a couple of screen shots as I don't know a better way:

    Left is the regulator depicted in the top schematic with VSwitched coming in the bottom and VSys leaving the top. Faint outline is my doing to show the regulator position relative to the pads and white dot represents pin 1

    Right, top side of the board is the second regulator. They are separated by about 3 cm and connected through a power plane. Orientation is rotated 90 degrees but pin 1 is still denoted with a white dot.

    As for screenshots of waveforms that will be trickier as my technicians have already blown off all the first stage regulators. If important for support we can try to remake one although not without some effort.

    Lastly we do have an efuse in series with these regs. I took a bit of a short cut to ask the question but think it is a different problem that we'd previously "solved" with the two regulator solution.

    Part of our system transiently draws up to 3A and the voltage sag was sufficient to upset the microcontroller thus we added a secondary regulator specifically for the uC. The complete system diagram is attached below with the first regulator going from battery to VSys. Vsys supplies our transient 3A load as well as the input voltage to the uC regulator (2v8) 

  • Hi General:

    Thanks for your information. The waveform is important to help the debug, please try to get that. And I prefer to check:

    1. Two converter cascaded: catch the Vin, Vsys, V2V8 waveform. With and without load.

    2. Power supply+second converter: same signals, with and without the load.

    3. For the cases which can't regulate 2.8V: Measure Vsys, L1, L2, Vfb of the second IC. 

    May I know why you add C104 and C83? If there is no particular reason, you could remove if before do the test.

    Additionally the layout is importance to ensure the switching power performance. According to the layout you showed, the caps are far away from the IC. For a buck-boost converter, the input and output caps should be put as close as possible to the ICs, and make the trace shortest. You could check the layout guidance of the datasheet or take the EVM layout for reference.

  • Hi General:

    As long time no hear from you, I assume you have solved the issue. If not, just reply below. Thank you!