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Part Number: TPS7H3301-SP
The TPS7H3301HKR datasheet says VTTREF buffered reference = ±15-mV accuracy. But the JEDEC standard says VTTREF has a required range of 0.49 * VDD to 0.51 * VDD. For a VDD input voltage of 1.35V - which the datasheet says is allowed - the JEDEC limits are 0.6615V to 0.6885V, or 1.35V/2 ±13.5-mV. So the JEDEC specification is tighter than the device specification.
Is there something I am missing here? Is there an argument as to why the IC is acceptable in this application?
You are correct, the device falls within the JEDEC specifications up to DDR3. DDR3L with lower voltage no longer meets the +/-1% tolerance.
However, I believe some additional margin is available if the module is not a traditional DIMM module as the JEDEC spec was designed for.
It is likely that a use case in space will not have a DIMM socket,and additional interconnect required for a socket, but will have memory "module" on same board as the terminator and controller. This is difficult to estimate the gain in margin with this improved interconnect.
I can work with you via email to provide some options on improving this margin for a DDR3L design.
I will send you a direct email to discuss.
If this answers your question, please click "This Resolved My Issue"Regards,Wade
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