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TPS2662: /FLT pin

Isacco Bressan
Prodigy 20 points
Part Number: TPS2662

In the datasheet at page 17 I read: "When the voltage at UVLO pin falls below V(UVLOF) during input power fail or input undervoltage fault, the internal FET quickly turns off and /FLT is asserted".

Is that correct?

The /FLT pin should be active low, so when it is LOW we have a fault, wher HIGH we have a POWER-GOOD condition.

So the previous sentence should be "When the voltage at UVLO pin falls below V(UVLOF) during input power fail or input undervoltage fault, the internal FET quickly turns on and /FLT is asserted"

Isn't it?

  • 0
    TI__Guru* 95791 points

    Hi Isacco,

    Welcome to E2E forums!

    I understand what you meant. The internal FET we refer in that sentence is the pass FET / Power FET (from Vin to Vout), which is turned OFF due to UVLO event.

    Please let me know if it is not clear.

    By the way, what is your application use case and system specifications ?

    Best Regards, Rakesh

  • 0 in reply to Rakesh
    Prodigy 20 points

    Great!

    Now I understand! It's clear!

    I'm designing a monitoring system for milling machines head attachments.

    The system power supply specifications are:

    Nominal voltage: 24V

    Minimum voltage: 21V

    Maximum voltage: 27V

    Maximum current: 250mA

    The milling head will be connected and disconnected from the machine and so the 24V power will appear and disappear at my board supply input.

    I would like to use the /FLT rising edge to wake up the microcontroller from sleep mode and the /FLT level as a "power-good" signal during normal operation. Again the /FLT falling edge will be a "go to sleep" interrupt. (the microcontroller is battery backed up).

    What do you think about this use of /FLT pin?

    Thanks and Regards, Isacco

  • 0 in reply to Isacco Bressan
    TI__Guru* 95791 points

    Hi Isacco,

    Thanks for the details.

    yes, /FLT output can be used as "power-good" signal 

    Best Regards, Rakesh