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TPS53353: How the ESR of output capacitor affect the stability?

Part Number: TPS53353

The datasheet shows the ESR and Cout of output capacitor should satisfy the condition below, but I don't know why. what is the detailed theoretical basis of this condition?

  • Jayden,

    Do you mean Formula 6? which means ESR zero is recommended to placed at f0(Bandwidth), and to ensure stability, 1/4 Fsw BW is recommended.

    Yuchang

  • Yuchang,

    Yes, it is Formula 6.

  •  

    The TPS53353 converter uses TI's D-CAP mode Adaptive Constant On-time control.

    D-CAP mode control functions by generating an On-time that is set by VIN, VOUT and the desired switching frequency, which charges the output voltage, then waiting for the output voltage to discharge back to the reference point before generating another, fixed on-time.  In order to maintain a stable switching frequency, this architecture relied on the output voltage ripple being "In Phase" with the switching node and inductor current.

    The Output Voltage has 2 output voltage ripple components:

    The Resistive output ripple is the Inductor Ripple current flowing through the output capacitor's ESR, and has zero-phase lag from the inductor current.

    The Capacitive output ripple is the Inductor Ripple current flowing through the output capacitor's capacitance, which has a 90 degree phase lag from the inductor current.

    Maintaining the ESR zero, 1 / ( 2 x Pi x ESR x Cout ), less than or equal to Fsw / 4, ensures that the phase angle of the output ripple is sufficiently low to maintain a stable switching frequency.  With higher ESR zero frequencies, the phase lag between the switching and the output voltage is higher, and the converter can operate alternating between two different frequencies that average to the target switching frequency, such as a converter programmed for 500kHz operating with pulses repeating at 1.5us and 2.5us instead of one pulse every 2us.

    If you would like to use the TPS53353, or other D-CAP mode controller, with less output voltage ripple or a higher frequency ESR zero, here is the link to the TI application note about using an external RCC injection network across the inductor to emulate a higher ESR and maintain stability with capacitors with very high ESR zero frequencies 

    https://www.ti.com/lit/pdf/slva453 

     

  • Peter James Miller

    In my mind, ESR x Cout > 0.5 x Ton, as long as this condition is satisfied, the pulse bursting phenomenon caused by out of phase ripple would be avoided.

    While, 1 / ( 2 x Pi x ESR x Cout ), less than or equal to Fsw / 4, which can be simplified as ESR x Cout > 2Ton/Dpi, which is obviously stricter than the condition above.

    So I don't understand why we must satisfy the second condition instead of the first conditon. And what is the detailed derive process of the second conditon.

    Thanks.

  • Hi Jayden

       Peter will get back to you on this on Monday.

    regards,

    Gerold

  •  

    Yes, the strict mathematical border of stability is ESR x COUT > Ton(max)/2

    The ESR zero Frequency < Fsw/4 is a generalized equation that removes maximum duty cycle to simplify the design process while providing design margin for ESR and Capacitor tolerance.