Hi team,
When the load is changed during low voltage battery, we can observe 2 states like below (VBUS is unconnected).
Could you estimate why 2 states can be observed although similar situation?
Pink shows Vsys waveform and green shows VBAT waveform which is 3V biased (cramped voltage of green is 2.5V).
Blue and yellow is just output of DCDC at secondary stage.
If you need more info, please let me know.
Best regards,
Koyo