TPS548B22: Related Thread: Reopen of Issue with TPS548B22

I Measured across one of the output cap using pigtail technique, you were true, output is as below.

but what i could not understand is 

i was expecting it to be a a pulse and then discharging curve with in limits, but rather how come its perfectly a pulsating with a PRF, is this the expected ouput ? or still there is noise coupling somewhere ?

but how should i check what is reaching the FPGA core, has it got coupled with noise ? i only have a test point of core voltage.

Hi Shyam,

Glad to see that the different measurement improved the result.

This type of output ripple waveform is dominated by parasitic ESL of the output capacitors and PCB. There is an inductive divider from the switching node to the output. With relatively output inductance value, the inductance between the output and ground becomes more significant. For example with only 300 pH effective inductance in series with the output caps, you would expect to see 12V*0.3nH/(200nH + 0.3 nH) = 18 mV. With lower output inductance it doesn't take much parasitic inductance to cause more output ripple.

To reduce the ripple, try to reduce the parasitic inductance in the PCB layout and/or use ceramic output capacitors with smaller package sizes. Smaller package sized ceramic capacitors should have less parasitic inductance.

Generally I would expect the ripple at the FPGA core to be slightly lower than measured near the output of the converter. Parasitic impedance of the PCB traces can provide a small amount of additional filtering. I suggest measuring as close as is practical to the FPGA.

One more issue i am currently facing is how to use the pgood for enabling other device like PMIC

is it mandatory to tie it to BP ?

rather can i pullup it with  a 3v3 rail of PMIC ?

if i pull up it to BP, the voltage read is 5v, which cannot be tolerated by the enable pins of pmic

kindly suggest a way out