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LM1117: Output capacitor ESR range is 0.3 - 22 ohm which is fine but how to reason about decoupling caps at load?

Gunnar Alm2
Prodigy 30 points
Part Number: LM1117

Hello,

Using the LM1117 as an example I want to hear your opinion on this?

I am making sure I meet the LM1117 requirement of 0.3 - 22 ohm ESR on my 22 uF output capacitor and I do the layout as suggested with the shortest and widest possible traces. But then my +3.3V rail goes on to the loads and these loads have e.g. a bunch of 100nF 0402 ceramic decoupling caps each having an ESR as low as 30 mohm.

In the case of relatively low static currents (<200mA) and small transients I have historically kind of forgot or even ignored about this ESR and capacitance contribution.

How do you reason reason about this ESR and capacitance contribution?

Regards,

/Gunnar Alm 

  • 0
    TI__Mastermind 29320 points

    Hi Gunnar,

    This is a very common question.  I am in the process of writing a new white paper on this topic, which will be available in the next year.
    The requirement on the output of the LDO basically looks like an impedance when you think of the ESR and capacitance requirements.  If you calculate the impedance across frequency of a series RC circuit which corresponds to the C and ESR of the output, that gives you a set of impedance curves your load must stay within to meet the datasheet specification. 

    Having said that, there are many linear regulators designed before low ESR ceramic capacitors.  In these cases the ESR forms a zero in the feedback loop which helps to stabilize the system.  In your case there are decoupling capacitors which will change the load impedance at some upper frequency.  If they are very small decoupling capacitors, then the load impedance will be unaffected until some very very high frequency (well beyond the bandwidth of the LDO) and it is not an issue.  This brings up another point - the capacitor and ESR spec are only for the crossover frequencies of the internal loops of the LDO.  A reasonable estimate of that is 10Hz - 10MHz for modern linear regulators, and this may tighten a bit for old linear regulators.  If the decoupling capacitors change the impedance within the 10 Hz - 10 MHz frequency range, then the LDO may be unstable so a test needs to be conducted to check for that.  This test is usually done on an EVM if the customer hardware has not been built yet.  A load transient test is the best choice as the phase margin of the system can be estimated accurately based on the number of rings in the transient response.  See the following link for additional details.

    www.ti.com/.../slva381b.pdf

    This is an overview but let me know if you have any questions.

    Thanks,

    - Stephen

  • 0 in reply to Stephen Ziel
    Prodigy 30 points

    Thank you Stephen,

    I am looking forward to your white paper.

    I have a working design with the LM1117 and a 22uF output cap with an ESR of about 0.5 ohm (0.32 ohm guaranteed) as stated in the LM1117 datasheet. This LM1117 feeds three small FPGA's consuming max 200 mA of current with small transients. Measured ripple is about 20 mVpp measured with a "simple" 7pF probe with a 2 inch ground lead. To me it works fine but I am requested to prove that the 75 pcs of 100nF 0402 MLCC's have been taken into consideration in the design and I do not know how to do that. The design is inherited and it is not known how the design was done, I know the output capacitor calculations have been done but I do not know if the many decoupling caps have been taken into account.

    You write "If they are very small decoupling capacitors, then the load impedance will be unaffected until some very very high frequency (well beyond the bandwidth of the LDO) and it is not an issue.". What is the bandwidth of an LM1117 and how small is a very small decoupling cap?

    I will not bother you with more questions after this.

    Thank you!

    /Gunnar

  • 0 in reply to Gunnar Alm2
    TI__Mastermind 29320 points

    Hi Gunnar,

    The LM1117 is at least 20 years old and it would be very challenging to locate design files to simulate the bandwidth.  Let's use 10 Hz - 10MHz as an estimate, although this is probably conservative.  By the way, if you conduct a transient test and observe the rings, the total system crossover frequency can be determined by looking at the period of the ringing.

    What you need is the effective impedance on the output and to calculate that you will want the manufacturer spice model of the decoupling capacitors and main capacitor.  You can then place them into a spice simulation and compare against the LM1117 specification.  The LM1117 specification can be seen in the following images.  Unless I missed it, this older device does not require a maximum capacitance, only a lower capacitance value of 10uF.  So on the high end of the impedance curve you will want to stay below the 10uF + 22 ohms impedance.On the lower end you will want to stay above 0.3 ohms (I included a 1mF capacitor + 0.3 ohms to show you what that would look like if you had that as a load).

    In sum: Simulate your load impedance with the manufacturer capacitor models in spice (you can use a free copy of TI spice if you do not have a spice simulator).  Stay between the red line and blue line and according to the datasheet, you are stable.  If you find your impedance falls outside of this, you can test the actual design with a load transient test to determine stability.

    Thanks,

    - Stephen