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ISO5852S: Questions about /FLT pin.

Part Number: ISO5852S

Hi. This is Jaehoon Kim from Seoultech.

During the development of 3-level SRC(Series Resonant Converter), The gate drive continues to fail.

So i want to ask you a question.

Topology : 3-level SRC

Switch : C2M0045170D [CREE/1700V SiC MOSFET] * 2 parallel

when the Output voltage of converter over 1kV, the gate IC  sends the FLT signal. but the Vds and Vgs waveforms of SiC are very good.

After that, the FLT, GND1, and IN+ pin are connected inside the gate IC.

I attached the gate drive schematic, please advise.

if you need any other information, Please ask.

Thanks.

  • Hi Jeahoon,

    Welcome to E2E!

    I have a couple questions that will help me understand and troubleshoot your application better:

    1. You mention when the output voltage converter is over 1kV the issue appears. Is the threshold where the error starts appearing? (i.e.with lower than 1kV the issue does not appear?)
    2. Would you be able to share the waveforms you mention of Vds, Vgs, , FLT and IN+ at the time of the fault?
    3. Could you explain why you placed component Z1 in your circuit?

    As an initial test could you disconnect the DESAT pin from the circuitry, connect this pin directly to GND2, and retest to see if FLT will still trigger.

    Best regards,

    Andy Robles

  • Thank you for your reply.


    1. Yes, the issue appears near 1100Vdc, and the secondary side gate driver is broken. Since it is a 3-level converter, the Vds at that time is about 550Vdc. It works well below that voltage.

    2. I measure only Vds, Vgs waveforms, and the Fig.1 is just before the error occurs.
    As you can see, the converter achieves a ZVS turn-on, and it's working fine.

    3. I wanted to use desat protection when 100A is flow to the FET.
    Fig. 2 shows the process how I selected Z1. If it's wrong, please let me know.

    please advise.

    Best regards,

    Jaehoon kim

    Fig.1

    Fig.2

  • Hi Jaehoon,

    You calculation is correct and the detection voltage would be ~5.5V.

    For the scope capture would yo be able to capture the FLT signal going low as well as the signal on the DESAT pin?

    • The timing of the signals will help me understand what could be root cause of your problem.

    Best regards,

    Andy Robles

  • Thank you for your reply.

    I measure the primary Switch Vgs, V_DESAT, V_FLT.

    I use NOT GATE after FLT signal. So V_FLT is LOW in the waveform.

    The V_DESAT of TOP switch is increase at dead time period.

    How can I resolve this problem?

    please advise. 

    Best regards,

    Jaehoon Kim

  • Hi Jaehoon,

    Thank you for sharing this information. I will need sometime to review this new information, and can get back to you by tomorrow 9/25.

    Best regards,

    Andy Robles

  • Hi Jaehoon,

    We're still reviewing the information you provided and expect to hear from Andy early next week.

    Regards,

    -Mamadou

  • Hi Jaehoon,

    Thank you for your patience. Can we go ahead and continue this conversation via email. Please reach out to a-robles@ti.com

    Best regards,

    Andy Robles

  • To. Andy Robles,

    Thank you for your reply.

    Ok. I will send an email to you.

    Best regards,

    Jaehoon Kim