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BQ25792: Is it possible to design a 2-layer board?

Part Number: BQ25792

Hello!!


Confirmed the new board layout of EVM.

There seems to be an improvement that lowers the output impedance compared to the previous layout.

By the way, I made a prototype board with 2 layers instead of 4 layers, but it doesn't work.

There is no doubt that the two-layer board is disadvantageous in terms of impedance.

Is it decisively difficult to make it with a two-layer board?

The cause of the board not moving is unknown.
Since STAT is blinking, it seems that something is wrong.
In order to find the problem, the battery is not connected to the BAT pin and the load is not connected to the SYS terminal, but the set voltage is not output.
The current is about 1A at 5V, and the chip is heating.
Therefore, it cannot be investigated carefully.
The resistance value between the BAT pin and GND is about 13Ω, and it may already be broken.

It seems that the same result can be obtained by mounting a new chip.
I haven't found any mistakes in the board layout.

Isn't it recommended to use it on a two-layer board? Or is it completely inoperable?
If not possible, I would consider a 4-layer board design or another chip.

Thank you.

  • Hi,

    We have not tested the chip on a 2-layer board.  The 4-layer PCB layout for the final EVM is attached.  You must ensure that the path from PIMD to GND and BAT to GND for the recommended capacitors are very low impedance (i.e. on the same layer as the IC with no vias), which will require that the SWx pins are routed down to the other layer with vias).  Also, the REGN and BTSTx traces to their capacitors must be low impedance (i.e. only via on one side of capacitors).  If you can do that, while still getting the low power and digital traces out using only 2 layers, then a 2-layer might work.6180.BMS034A_TIS_PCB.PDF

    Regards,

    Jeff