This thread has been locked.
If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.
UCC28019A: Input Current Distortion when a load is connected
Part Number: UCC28019A
My customer is evaluating UCC28019A and has a question.
I would be grateful if you could advise.
We are evaluating UCC28019ADG4.
Noise is observed in VDS and VGS of Q1 and Q2 when the MOSFET is turned on.
Could you please attached excel file.
UCC28019ADG4_FET VDS_VG noise_20200930.xlsx
The waveforms are shown in Fig. 1 (when the load is ON) and Fig. 2 (when the load is on).
We confirmed that the gate signal is already noisy at Gate pin output (8pin) ,(Checked with TP20 in the circuit diagram)
Could you please let us know the cause and countermeasures for this noise?
I appreciate your great help in advance.
Thank you for your interest in the UCC28019A PFC controller.
The UCC28019A GATE pin is not the source of the ringing. I suggest that the origin of the high frequency noise at the MOSFET gates in Figure 1 is due to reverse recovery of the output diode D6.The case in Fig.1 is at high current through D6, and when Q1 & Q2 turn on, the Vds high dv/dt corresponds to when D6 stops reverse recovery current and snaps off. This results in ringing between the parasitic drain capacitance and the boost inductance. In the case of Figure 2, the diode current is very low so reverse recovery is softer and no ringing occurs. The high dv/dt of Vds does pull gate current through the Crss (same as Cgd) of the MOSFETs which causes the small step in the Miller plateau of Vgs.
For the ringing at high current, a ferrite bead in series with D6 can suppress the high frequency, however such a bead needs to sustain the peak current and not saturate. This will be a large expensive bead. Putting smaller beads in series with each MOSFET gate can reduce Vgs ringing but will not stop Vds ringing. Instead, an R-C snubber across D6 can help damp the ringing but will also increase switching loss. The schematic shows two snubbers across Q1 and Q2, but these are ineffective.
I suggest to reduce the capacitance of C101 and C102 to 470pF each and apply the difference to a snubber cap across D6. The three snubber resistors will have to be re-tuned for optimal damping. But the total switched-node capacitance will not be increased so switching losses will stay the same.
We are glad that we were able to resolve this issue, and will now proceed to close this thread.
If you have further questions related to this thread, you may click "Ask a related question" below. The newly created question will be automatically linked to this question.
All content and materials on this site are provided "as is". TI and its respective suppliers and providers of content make no representations about the suitability of these materials for any purpose and disclaim all warranties and conditions with regard to these materials, including but not limited to all implied warranties and conditions of merchantability, fitness for a particular purpose, title and non-infringement of any third party intellectual property right. No license, either express or implied, by estoppel or otherwise, is granted by TI. Use of the information on this site may require a license from a third party, or a license from TI.
TI is a global semiconductor design and manufacturing company. Innovate with 100,000+ analog ICs andembedded processors, along with software, tools and the industry’s largest sales/support staff.