Dear TI-support team,
I´m trying to simulate the circuit for the gate driver UCC21750 with LTSpice XVII, but I have problems with the OUTL and OUTH signals. In the appendix I send you a screenshoot of my current status (schematic and measurement results), but here is the problem, that there is no output signal for the signal CANL or CANH.
My guess is that the enable signal is missing, but if I connect the RST_EN pin with a 5V signal the LTSpice project cannot be compiled and the programm crashes.
What am I doing wrong with the simulation?
I would be very happy, if you have a solution for my problem.
Thanks in advance,
Best regards
Michaela