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UCC21750: Simulation with LTSpice

Part Number: UCC21750

Dear TI-support team,

I´m trying to simulate the circuit for the gate driver UCC21750 with LTSpice XVII, but I have problems with the OUTL and OUTH signals. In the appendix I send you a screenshoot of my current status (schematic and measurement results), but here is the problem, that there is no output signal for the signal CANL or CANH.
My guess is that the enable signal is missing, but if I connect the RST_EN pin with a 5V signal the LTSpice project cannot be compiled and the programm crashes.

What am I doing wrong with the simulation?

I would be very happy, if you have a solution for my problem.

Thanks in advance,
Best regards

Michaela

  • Hi Michaela,

    Welcome to E2E!

    Sometimes simulation are tricky to get working properly. One thing i notice is in your simulation V(rst) signal is kept low. In the schematic i only see a label on the RST pin and not anywhere else in the schematic. This pin should be pulled high for proper operation.

    If pulling RST high doesn't work let me know, and I will try simulating your configuration on my end to see what else could be going on.

    Best regards,

    Andy Robles

  • Hi Mr. Robles,

    thank you for your answer.

    I already tried to pull the reset_enable pin high, but then my simulation complies more than 3 hours without a solution and crashes.

    Do I have to pull the reset_enable pin the whole time high or is it just an impulse?

    I would be very happy if you could try to simulate my configuration and give me feedback.

    Best regards,

    Michaela

    P.S.: I attaced my ltspice simulation.UCC21750_simulation.zip

  • Hi Michaela,

    I will take a look into your simulation as it should not take that long to compile. I will be busy for the rest of the day so i won't be able to look into this until early next week. Please reach out to me via email so we can continue troubleshooting your problem.

    Best regards,

    Andy Robles