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Original question:

TPS650861: Routing of DRVHx and SWx

TPS650861: Routing of DRVLx

Dice-K
Mastermind 6330 points
Part Number: TPS650861
Other Parts Discussed in Thread: CSD87381P,

Hi support team,

Due to the terminal position of TPS650861 and CSD87381P, DRVHx and DRVLx of BUCK1 and BUCK2 intersect.
Prioritizing DRVHx and SWx, DRVLx should be submerged in the lower layers.
Is this the best way?

The following condition cannot be kept.

TPS65086x Design Guide
www.ti.com/.../slvuaj9.pdf
3.3 PCB General Layout Check List, Page-12, SLVUAJ9

"DRVLx signals must be routed on the same layer as the IC and the FETs and minimize the length and
parasitic inductance of the trace as much as possible."

Regards,
Dice-K

  • 0
    TI__Genius 17380 points

    Hello,

    I would recommend prioritizing the DRVLx signal instead of the DRVH signal, but in the 5 years I've been supporting this device I have not seen any issue linked to the DRVH/DRVL/SWx signal routing. 

    The reason to prioritize DRVLx is minor, my understanding is that it's just preferred for the low-side FET to be the most optimal since it is responsible for normal operation and overcurrent operation. The impact I think is so minor that I don't generally recommend changing the layout if it is at least close. The controllers were designed for up to 20 cm distance between PMIC and FET.