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UC2825A: Unable to produce output pulses

Part Number: UC2825A

While trying to develop a series of tests to allow the electrical characteristics of the device to be tested, we found we were unable to produce any form of pulsed output as expected.

The test circuit used to test the part was the one suggested in the "Open-Loop Test Circuit" for the UC2825-EP (SGLS305D). After constructing the circuit as shown, we were able to confirm the waveforms for the CLK/LEB pin, CT pin and ILIM/SS section were functioning as expected. However the output remained at a constant near 0 (<300mV) or high (~13V).
The EAOUT pin was a DC waveform of around 120mV and therefore never crossed into the threshold of the RAMP waveform (to enable the function of the PWM Comparator (as shown in the block diagram).

Researching online we came across SLUS235A, which provided an alternate Open-Loop Test Circuit, however in a similar fashion this also proved unsuccessful with the EAOUT now showing a DC waveform of around 5V (above the RAMP) and the outputs once again being a constant voltage near 0 (<300mV).

Is there something we are doing wrong to produce the expected pulses at the output? Have we forgotten a key component of the circuit or is there possibly something wrong with the circuit diagrams we are using (possibly a printing error)?

Thank you for your time and help

  • Hello! 

    Thank you for reaching out and for your interest in the UC2825A! I will reach out internally to our team and see if there are any known issues with the figures & documents you referenced. While I do that, can you try swapping in another IC and see if you're able to replicate the same behavior? 

    Thanks again for getting in touch and bringing this to our attention, I look forward to talking more soon! 

    Aidan Davidson

  • Morning Aidan,

    After initially seeing the error, we swapped the IC for another previously unused (fresh from the packaging) IC and the same behaviour was seen.
    Both ICs have otherwise performed nominally in the VRef, Oscillator measurements, Error Amplifier measurements, ILIM/Soft Start measurements etc.
    The slight increase in voltage (to the aforementioned 300mV also adhered to the behaviour described in the UVLO section.

    It seems to only be the production of the output pulses which doesn't seem to work, which from my understanding would be because of the biasing of the EA amplifier section in the test circuit placing the EAOUT pin above or below the Vramp and therefore not causing the PWM comparator to switch at any point.

    Thanks

  • I'm still waiting on feedback from internal teams, in the mean time I will review the open-loop schematics you've mentioned here to see if anything jumps out. I'll try to get you a response by the end of the week! 

    Best, 

    Aidan

  • Thank you for your help Aidan, I await your reply.

    Regards,

    Jorn

  • Hi Jorn! 

    Thank you for your patience on this issue! Can you try reducing the boxed resistors (22k, 10k, 3.8k) below by a factor of 10 (2.2k, 1k, 380)?

     Thanks again for getting in touch, I hope this resolves your issue! 

    Aidan Davidson

  • Hi Aidan,

    Unfortunately after implementing the above changes the result ended up being much the same. With regards to the above schematic, it's unclear to me why both inputs (INV, NI) would be shorted together and fed back by the EAOUT. Is this supposed to produce a specific bias level at pin 3 (EAOUT)? Is my thinking correct in that to produce an output pulse the bias level at pin 3 (EAOUT) should sit somewhere within the voltage range of pin 7 (RAMP)

    I have taken some screenshots of the oscilloscope on various pins/pin combinations to try and see if any of that helps make sense of our problem.

    Firstly, I have taken a screenshot of pin 8 (SS, Yellow trace) and pin 9 (ILIM, Blue trace). As expected when pin 9 (ILIM) is <1V pin 8 (SS) is at 5.1V. However in the current configuration Changing the 1kOhm pot has had no effect on pin 9 (ILIM) and I am unable to trigger the SS reset.

    The second screenshot I have captured shows the traces at pin 3 (EAOUT, Yellow trace) and pin 7 (RAMP, Blue trace), both of which feed into the PWM comparator in the internals of the device. I would expect based on the device block diagram that pin 3 (EAOUT) should sit as a DC voltage within the voltage range of pin 7 (RAMP) for the output to produce a PWM signal, and as seen below, the voltage level at pin 3 (EAOUT) being below the entirety of the trace at pin 7 (RAMP) causes the outputs to be forced high for 100% of the duty cycle. I'm unsure as to what the little peaks in the trace of pin 3 (EAOUT) are, but they seem to be as long as the falling edge of the signal at pin 7 (RAMP)

    Finally, for completeness, I have taken a screenshot of the traces at pin 1 (INV, Yellow trace) and pin 4 (CLK/LEB, Blue trace). The signal at pin 4 (CLK/LEB) is exactly as the data sheet proposes and I have good confidence in it's function. The DC voltage value at pin 1 (INV) is also exactly half VREF as expected and seems to be correct.

    With the above information, I'm not entirely sure why although the signals leading up to the PWM comparator seem to behave as expected however no output signals seem to be produced. The only reason for which I can guess is that the DC voltage level at pin 3 (EAOUT) isn't within the voltage range of pin 7 (RAMP).

    I hope this additional information helps paint a clearer picture of the issue I'm having.

    Thanks,

    Jorn

  • Hi Jorn, 

    Thanks for the further details on your issue. I'm going to work on some simulations on my side of things and try to get you a solution, I'll get back to you Thursday latest. 

    Aidan

  • Hi Jorn, 

    Apologies for the delayed response and thank you for your patience. Unfortunately I haven't been able to get an open-loop sim working for you, I'm going to keep working at it and get back to you on Wednesday with an update. 

    Thank you, 

    Aidan

  • Hi Aidan,

    I've been working on some possibilities on my side and have had a bit of a breakthrough which is promising.
    By implementing the below circuit (although I have had to make a small change) I was able to see an anti-phase square wave at the output of the device with a duty cycle of around 20%.
    To get a clean output I had to sever the connection between pin 11 (OUTA) and pin 14 (OUTB). Maybe this will help find an explanation to the open-loop circuit.

    Thanks,

    Jorn

  • Hi Jorn, 

    Since we've moved to communicating through CSC, I am closing this thread. 

    Thanks, 

    Aidan