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Part Number: TPS7A78
I have a design using TPS7A7833PWPT in HB mode. Intermittently it powers up and LDO_OUT is 1.7V rather than 3.3V. I suspect it may have to do with me violating the Cldo_in/Cldo_out 10:1 ratio. My circuit values are as follows:
TPS7A78 in HB mode
Cscin: 330uF + 100nF
Csc1: 1u +100n
Csc2: 2.2u + 100n
Appreciate if you can...
1. explain the my intermittent 1.7V on LDO_OUT.
2. explain the 10:1 ratio requirement
3. how to calculate hold time for the TPS7A78 in HB mode. I assume on power outage TPS7A78 remains powered by Cscin?
Figure 22 shows how a load transient can trigger a startup if the Cldo_in capacitor is not sized properly. If a DMM is used to measure Vout, and a load transient is causing the device to repeatedly restart, then the DMM may be taking the average which could get you close to 1.7V. For this reason, please confirm the method of your measurement (DMM, oscilloscope) and please confirm your output current characteristics while you are seeing 1.7V.
When you say the LDO output is 1.7V, does it hang here without recovering, or does it eventually ramp up to 3.3V?
The 10:1 ratio allows the internal LDO to respond to load transients without experiencing a significant droop on the input supply, causing it to fall below UVLO value and accidentally trip off. This is important since the LDO is powered by a charge pump circuit so the large Cin cap can be thought of a hold up cap. If your load is low this is less of a concern.
The SCIN pin capacitor is used as the hold up capacitor when the AC supply powers down.
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In reply to Stephen Ziel:
thanks for the quick reply. Yes, my measurements were taken with a DMM, so as you say it could have been continually restarting.
The TPS7A78's load consists of...
a) 2off electricity meter chips (with integrated sigmadeltaADCs) - datasheet only gives typ operating current = 4.5mA per chip. These chips are not held reset on power up, but their internal POR circuit holds the chip reset until supply exceeds 2.5V.
b) 2off TI ISO7760 isolation chips - datasheet gives worst case max supply current =11.4mA per chip. But TPS7A78 only powers one side of the isolator, and one of the isolators is oriented with inputs on the TPS7A78 side and the other with its outputs on the TPS7A78 side.
So when the circuit powers up in its faulty state with LDO_OUT=1.7V (measured with DMM), it stays in this state ie does not eventually ramp up to 3.3V.
Some additional measurements taken, again with a DMM, are:-
DMM DC voltage measurement, while in good state, while in faulty state
Vscin, 16.47V, 16.05V
Vsc1, 8.22V, 7.54V
Vsc2, 4.06V, 3.48V
Vldo_in, 4.00V, 3.47V
Vldo_out, 3.3V, 1.7V
In reply to tc:
The values when the device is not operating properly give us a lot of hints as to what is happening. We would need some oscilloscope plots to confirm what exactly is happening here, including current probe measurements to confirm the peak value of the load transients.
The Vldo_in voltage is measuring 3.47V when it is not operating correctly, I think this is probably due to load transients or a heavy load current on the output of the LDO causing this voltage to droop. Working ourselves backwards, the output of the second flying capacitor in the charge pump is drooping (3.48V instead of about 4V), and so is the first flying capacitor (7.54V instead of about 8V). The droop on the charge pump is a strong hint that it is experiencing a heavy load as well.
The Vscin voltage is above 16V in all cases. What should be happening is: Vscin is roughly 16V, Vsc1 is roughly 8V, Vsc2 is roughly 4V. Because the Vscin voltage is where it should be, this tells me the front end of the design is probably sized properly.
Can you place >10x the LDO_out capacitor on LDO_in and see if the issue goes away?
thanks, that makes sense. Ok, let me try increasing capacitance on LDO_in.
Just a couple of things I'm not clear on...
1. Do I really need to meet the 10:1 ratio or is it ok to simply increase capacitance on LDO-in? My circuit at the moment has approx 32uf (10u //l 22u) on LDO_in and 45uF (22u //l 22u //l 1u) on LDO-out. Constrained by components I have available at the moment, I could a) add 2 more 22uf caps to LDO-in to get approx 76uf, and leave LDO-out, as is, with 45uf or b) 76uF on LDO_in and decrease capacitance on LDO-out to 4.7uF to achieve approx 10:1 ratio. Is there an issue with option (a)?
2. Still not sure how to work out the holdtime - can you please provide details.
would increasing the capacitance on SC1 and SC2 (I understand it will increase startup time) help, or makes things worse, in my situation, which appears to be high current load on startup?
I ran some SIMPLIS simulations with your component values, I estimated the AC voltage as 120 VAC but let me know if that should be 240 VAC or another value. I used 30mA load on the output (modeled as a pure resistor). As expected, during startup the LDO_in cap is drooping enough to fall below the UVLO threshold of 3.5V causing the LDO output to collapse. This then repeats itself forever: LDO_in charges up, the UVLO threshold is exceeded and the LDO turns on, following by a rapid transfer of charge from LDO_in to LDO_out causing the LDO_in capacitor to droop below the UVLO threshold.
As shown, if you can reduce the capacitance on the LDO output and increase the capacitance on the LDO input then I would expect the issue to be resolved, however you will need to assess if the capacitance on the LDO output will be sufficient for any load transient requirements.
I then ran a simulation with:1. VLDO_in = (22uF * 3) // 10uF2. VLDO_out = 4.7uF // 100nF
This seems to work. Iout is still a 30mA load modeled as a resistor, and component tolerances are not taken into consideration.
If I leave all of the components in the simulation to what you described in your original post, but I change the flying capacitors SC1 and SC2 to be 4.7uF (max per the datasheet) the issue still does not resolve itself as shown in the simulation.
In regards to your questions:
1. The 10:1 is not listed as a hard requirement, but more of a guideline or best practice. As you can see from the simulations, the extra cap on LDO_in prevents the droop which causes the UVLO to be tripped. The charge pump can replenish the charge on the LDO input however the LDO input capacitor droops too much while the charge pump capacitors themselves are being replenished by CScin.
2. Once the AC voltage is removed the 330uF capacitor on CScin is your main energy storage, followed by the LDO_in capacitor. The charge pump will continue to deliver charge from CScin to the LDO_in capacitor but once the LDO_in capacitor droops below the UVLO threshold, the LDO output will turn off as we are seeing. So the hold time is a function of current draw on the LDO output removing charge from LDO_in and CScin, until the 4V on LDO_in ramps down to about 3.5V.
thanks so much for running the simulations - thats cleared things up. My application is for 240Vac not 120Vac, but I think all the info you provided is still valid - correct me if I'm wrong.
One last thing, regarding the hold time and the last simulation plot you provided... I assume that this sim was for a 30mA load. So as you say the hold time comes from the energy stored in Cscin and Cldo_in - I'll ignore Cldo_in because Cscin is dominant. So it looks like while the voltage at Scin is >15V, the charge pump is able to deliver current to Cldo_in, but below 15V charge pump stops. If I've done my calcs right using i=(Vo-Vi)C/t for constant current discharge, then hold time can be calculated as time for Cscin to go from 16.25V to 15V with constant current of Iout/4. ie t=(16.25-15)330u/7.5m=55ms. Is this right?
Yes you are correct, these simulations are still valid because the issue is not with the front end, it's after the AC voltage has been converted to about 16V on Scin. And yes your hold time math is basically how I would do it. I thought this was in the datasheet but I actually don't see it, I may need to write an app note on this to close the gap. The 55 ms approximation you calculated based on simulation data is very close to the simulation results.
It looks like the SIMPLIS model may have some slight inaccuracies, for instance the Scin voltage should be around 16V (not 16.4V as it appears to be) and the UVLO should trip at 3.5V or less (not 3.8V like the simulation seems to show). Figures 19 and 20 in the datasheet show how the Scin voltage hovers around 16V for reference. Per the datasheet the maximum (worst case) UVLO trip threshold is 3.5V on the internal LDO. The charge pump ratio is 4x. So the UVLO will trip when the Scin voltage is below 4*3.5 = 14V worst case. The steady state voltage on Scin is about 16V. So I would use the following math based on these datasheet values:dt = C * dV / I
dt= 330uF * (16-14) / 7.5mA = 88ms
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