UCD3138: How to synchronize the switching frequency of power modules

Hi,

Is this needed for a new project or an existing project?

What is the topology of your power supply and what is Event4 set to?

The SYNC pin in UCD3138 can be used for synchronization between the power supplies.

Please note that an edge on SYNC will reset the counter on DPWM and restart a new DPWM switching cycle on the receiving part.

Therefore the two frequencies are going to match.

But depending on your DPWM configuration, some restriction and considerations may apply.

Hope this helps.

Regards,

Hi,

1、it's an existing project;

2、we use hard-switching half-bridge;

EV4 is use to set the deadtime between primary mos and SR mos.

Dpwm0Regs.DPWMEV1.all = EV1;

Dpwm0Regs.DPWMEV2.all = ((PWM_PERIOD+EV1) >> 1)- DEADTIME1;

Dpwm0Regs.DPWMEV3.all = ((PWM_PERIOD+EV1) >> 1);
Dpwm0Regs.DPWMEV4.all = EV1 - DEADTIME2;
Dpwm0Regs.DPWMPRD.all = PWM_PERIOD;

3、I find there is a external sync enable bit in the DPWM control register. for the slave module，we need to enable this bit, right? But for the master module, how to set the sync signal？

Hi,

what's the meaning of  pulse extension?

And I noticed there is a paragraph about CBC and slave sync in the UCD3138 technical reference manual.

CBC_SYNC_CUR_LIM_EN is used to control the slave sync. If this bit is set, the slave sync is advanced
during current limit. This is not used in any topology configuration at this time. If this bit is set, the sync out
pulse from the DPWM will occur if the CBC fault occurs. If the CBC fault does not occur during a period,
the sync pulse will occur according to the normal setting of the sync control bit fields

If the bit is set to 1, the CBC fault will result in the sync out，right？

If the bit is set to 0，the sync pulse will just occur accoring to the normal setting, CBC fault has no effec to the sync pulse, right?

Hi,

As you know DPWM's B output goes low at Event4.

That is because when DPWM_counter reaches Event4 (DPWM_counter == Event4), B output toggles low.

If DPWM_counter resets due to the arrival of SYNC signal before Event4 is reached, then it will never reach Event4 during the current switching cycle, and B output will stay high.

Meaning the B pulse will extend into the next switching cycle (Pulse extension). That is obviously not a desired behavior and needs to be prevented.

I have no experience with DPCBC_SYNC_CUR_LIM_EN, this bit is always set to zero (default) in our applications. I will try to find out what is this bit for.

Regards,