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TPS3851: Questions about /WDO assertion

Si Yoon Kim
Intellectual 710 points
Part Number: TPS3851

Dear TI Team,

I have a question about the WATCHDOG TIMER IC.

As far as I know, if SET1 is set to LOW, WATCHDOG is disabled and /WDO is asserted as LOW.

Is there a case where /WDO is output high even if SET1 is LOW?

I couldn't attach the waveform, but /MR is High, /REST is also High, and SET1 is kept high for about 1-2 seconds, then becomes LOW, and WDI is switching to 3.3V voltage every 1 second. At this time, /WDO is kept high.

The circuit is roughly as follows.

Thank you.

  • 0
    TI__Intellectual 1695 points

    /WDO output high is normal (no fault) condition. /WDO low is fault (timer expired) condition (figures 1 & 2 in the datasheet). SET1 going from disable to enable has a startup window during which there will be no response to WDI transitions (Fig.23). Depending on which orderable is used (S or E in the name), for example TPS3851G33SDRBR vs TPS3851G33EDRBR, 1uF capacitor on CWD results in timeout of about 3.3seconds or 77seconds (Table 4 and Table 5)- is that the design intent?

  • 0 in reply to Ajay Padgaonkar
    Intellectual 710 points

    Dear Team,

    I'm very appriciate so much for your response.

    Yes, that's the design intent.

    And I also attach images to ask specific questions.

    As shown in Figure 1, during initial booting, SET1 is in high state for about 8 seconds, and then asserts to low.

    After that, after booting is complete, the WDI pulses every 2 seconds and as a result, /WDO=3.3V is output.

    Here, I want to ask you a question.
    As a result, SET1 is asserted as Low, but /WDO is output as High.

    Could it be that SET1 high output for several seconds during initial booting, could be the cause of making /WDO high??

    If so, can you elaborate on why?

    I am getting a lot of help for your answers.

    Thank you.

  • 0 in reply to Si Yoon Kim
    TI__Guru 56345 points

    Hi,

    Please see my answer in red below:

    As a result, SET1 is asserted as Low, but /WDO is output as High.

    When SET1 is asserted low, the watchdog timer is disabled and /WDO becomes high-Z state.

    Could it be that SET1 high output for several seconds during initial booting, could be the cause of making /WDO high??

    No, /WDO is high because the SET1 pin is pulled low.  When SET1 is pulled low, any input to the WDI pin is ignored.


    If so, can you elaborate on why?

    /WDO stays high when /RESET is low and /WDO will stay high unless it does not sense a falling edge of WDI within the timeout period (twd) for SET1=high.  See below:

    Ben