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UCC5390: Elimination of multiple power supplies for VCC2 and reason for Isolated gate drivers damage

Lingamurthy Komire
Intellectual 295 points
Part Number: UCC5390

Elimination of multiple power supplies:

We require three MOSFET switches and Isolated gate drives to control the motor as shown in the sketch. Each gate driver has to be provided with separate power supply (Vcc2) to maintain isolation. Please do suggest a solution to eliminate multiple power supplies.

Power on issue:

At power up, on reset of micro-controller, by default a logic high state glitch at the input (IN+) of gate drivers switching on the motor momentarily. It needs to be avoided. Please do suggest.

Gate driver damage:

Motor rated voltage - 110V DC, Split field series, rated current - 5A, peak current - 8A.

PWM frequency to drive the motor - 10KHz with a duty cycle resolution of 2% and step interval - 100ms. Approx 4.5sec is the duration to reach 100% duty cycle.

470uF/100V capacitor is placed across 110V supply to suppress the noise.

When start driving the motor with PWM we have observed high current is drawn by the VCC2 power supply. Later came to know that Gate drivers (I1 and I2) have been damaged. Investigating the issue. Please do suggest.

While testing coupling capacitor at MOSFET gates has been removed. 

  • 0
    Intellectual 295 points

    Q1 is connected to Forward terminal of the Motor,

    Q2 is connected to common terminal of the motor,

    Q3 is connected to Reverse terminal of the Motor.

  • 0 in reply to Lingamurthy Komire
    TI__Guru**** 189399 points

    Hi, Lingamurthy,

    This app note discusses how to use the IN pins as an enable. You might be able to implement something like this to solve your turn-on glitch issue.

    Effective decoupling of the supplies for our gate drivers are critical. You don't show any decoupling on your schematics.

    What is the purpose of the 4.7 uF cap in series with the gates?

  • 0 in reply to Don Dapkus
    Intellectual 295 points

    Hi Don,

    Thanks for reply. We do implement as suggested in app note to counteract the glitch.  4.7uF cap in series of gates is removed as it is not required.

    While testing, we set the motor supply as 24V (between BP and BN). We have observed undershoot of voltage at motor terminals while switching the MOSFETs. Does this undershoot is the reason for Gate drivers failure as we have not provided snubber ckt? or Are Gate drivers sinking more current (> 10A)? Now we stuck up at this stage. Please do suggest.

    Regards,

    Lingamurthy K.

  • 0 in reply to Lingamurthy Komire
    Intellectual 295 points

    Hi,

    As per the sketch, I1 is driving the Q1 with static high whereas I2 is driving the Q2 with PWM in order to run the motor in forward direction.

  • 0 in reply to Lingamurthy Komire
    TI__Guru**** 189399 points

    Hi, Lingamurthy,

    Yes, if you have voltage spikes that exceed the recommended operating conditions, this can cause the device to fail. Here are the absolute maximum ratings:

    In addition to tight decoupling, pcb layout inductance can also cause voltage spikes that exceed the Abs Max ratings and can potentially damage the device. Please reference the guildelines at the end of the datasheet for layout, and reference the EVM design for an example of a recommended layout.