Part Number: LM5101B
I try to design a class D op amp. The input sin wave has the amplitude of 1 V and 20K frequency with the 1V dc. The sawtooth waveform has the amplitude of 2V and 200k frequency. The mosfet I choose is IRF540. When I set the Vdd of the high side mosfet is 40V and low side is 0V, the system works well. But if I change it to symmetric system with Vdd of the high side mosfet is 20V and low side is -20V, the system does not work well. Does anyone know how I can fix this problem? I appreciate your help.
For simulation models, the driver ground pin, VSS, is expected to be at the circuit ground potential. Even though the IC will work with a ground reference at -20V, for simulation the ground of the IC needs to be at circuit ground and the voltages level shifted accordingly.
So for your simulation, the VSS should be at ground, and the FET positive supply level shifted from 20 to 40V as you have simulated so far. The driver input and output signals are expected to be referenced to ground, not -20V.
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In reply to Richard Herring:
Thanks for your help. I am wondering what I should do if I want to keep the low side source voltage to be negative? Is it possible?
In reply to Zhekun Liu:
For the real application circuit, the driver Vss pin can be referenced to a negative voltage as you show in your schematics, just make sure that the driver pin voltages, especially the LI and HI input pins are referenced to the same negative voltage as the driver VSS pin.
For the simulation to work, the voltages have to level shifted with the driver VSS referenced to the circuit ground for the model to work properly.
Confirm if this addresses your questions or you can post additional questions on this thread.
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