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UCC28950 asymmetric duty cycle operation at light load condition

woosup kim
Prodigy 10 points
Other Parts Discussed in Thread: UCC28950, UCC3895, UCC2895

Dear TI engineer

I've tested my 3kW DC-DC converter with your ucc28950 PWM IC.

However, currently I have unanymous problem.

At light load condition, Output C/D duty was not 50 to 50% but asymmetric ducy cycle.

I found application report ; slua275 ucc3895 OUTC/D asymmetric dyty cycle operation.

Plz check below questions

1. Detail logic block described in in ucc28950 datasheet is the same as which of ucc2895?

2. In slua275, it metioned, " Also, when using synchronous rectifiers in current mode operation this problem does not typically exist due to the additional reflected secondary current added to the primary side current sense.'. I couldn't understand why? Can you explain in datai?

3. Recommand me to escape this problem.. ( ramp pin is already located inside the PWM IC, I couldn't find any external method which you used in slua275.

  • 0
    Prodigy 20 points

    Interesting...I'm also seeing a similar  issue, I've raised a similar issue in the forum before reading this.

    in my application, C/D is not 50/50 but going to 40/50 with 10% deadtime. I'm even increasing the load.

    Hope TI responds to our inquiry.

  • 0 in reply to Dennis Martin
    Prodigy 80 points

    I'm faced to the same problem with the UCC3895 controller.

    Adding the suggested resistor from SLUA275 helps only to reduce the problem in my case.

    For easier investigation, I'm now running the controller in open-loop mode with no load.
    "EAOUT" und "EAN" are tied together.
    At "EAP I'm feeding a control voltage from an external power supply.
    The slope compensation signal is made by an additional ciruitry that is triggered from OUTA & OUTB signals to provide a sufficient sawtooth without load the timing signal.

    When I reduce the control voltage at the "EAP" pin, the C- & D-outputs gets asymmetric.
    The positve and negative pulse of the driving voltage of he transformer are differing and I get a large DC current through the transformer.
    Then my MOSFET driver for the C + D MOSFETs gets damaged.
    Because of that I'm now running my tests without powering the H-bridge...
    But I still don't know how to get rid of these asymmetric C- & D-outputs.

    In my application it is necessary that I can also use small duty cycles for a longer period.